Thread Details

  • State Verified Answer
  • Replies 1 reply
  • Subscribers 69 subscribers
  • Views 259 views
  • Users 0 members are here
Options
Related 

        

            Post
             Go back to editing
        

    

    


    

    









		


















	
	
			
	
			
		
	
	
		

	    
	    
	    		
ad4111采样频率问题

		
	
				

			

									
					    aaaqqq
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Aug 26, 2026 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user asked about the AD4111 ADC's output rate when using 8 channels with open circuit detection. The final answer clarifies that the 6.21 kSPS rate is for the entire chip, not per channel, resulting in approximately 776 SPS per channel. The engineer suggests using the sinc3 filter for higher rates or reducing the frequency of open circuit detection to optimize performance.
                        	    

                
                     AI Generated Content
                
    	    

             
				
        		

		    
		    		    
		    			

			    
AD4111，ODR设置为31250，使用开路检测要求的通道配置，用了8个通道，从手册的表6来看，它说能够实现6200sps per channel，但是实际fpga跑出来，连续转换模式下，adc的输出大约是6200hz，但是要被每一个通道平分，为什么
这芯片是单Σ-Δ adc核的，输出频率需要平分吗，问了FAE，又说可以每通道6200hz输出


			

			
									
		                             
                        

    

                                            
                 Analog to Digital Converters (ADCs)
                
                                                    
                 Multiplexed A/D Converters
                
                                                    
                 Precision A/D Converters
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

  • 
	
    



	
			
		
	



    
	
    
		
    
							
					
    
		
    
		    
		    		    
			
				
									
							        
			
			
			
    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Sep 22, 2026 11:27 AM
            
            
						
			                            
                     Contains AI Generated Content
                
            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    你的测量是对的。6.21kSPS是整颗芯片的通道扫描率（手册原文是maximum channel scan rate of 6.21 kSPS (161 µs) for fully settled data），表6那列"SPS per Channel"指的是切换通道后单次已建立转换的速率，不是每个使能通道能同时拿到的速率；8个通道槽轮流平分，6211/8≈776SPS，与你实测的775一致。反过来算也能确认：8路各6.21kSPS需要49.7kSPS，已经超过sinc5输出固定的31.25kSPS，单个Σ-Δ核做不到。
    

    还要注意开路检测本身的开销：手册要求每个电压输入在做开路检测时占用两个通道槽，所以这8个槽实际只对应4路物理输入，每路每秒约776次开路比较。
    

    提速有两条路：一是改用sinc3，最快档的建立时间是97µs、整体约10309SPS，8个槽下每槽约1289SPS（约1.66倍），代价是最高速率下噪声明显大于sinc5+sinc1；二是不连续做开路检测，平时每路只占一个槽，定期切到配对配置做一次诊断。
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

    • 

	





	
			








		

		

			
    
				
  • 
					
												
						
						
						
						
						
						
						

																										
						
						

					
					
					
				
    • 
			

		

	








































     



















		        
        

            
Before You Switch

            
        

        

        

            Switching languages will make ADI Explorer unavailable. Resume your session by switching back to English and reopening ADI Explorer.