Thread Details

  • State Verified Answer
  • +1 person also asked this people also asked this
  • Replies 4 replies
  • Subscribers 70 subscribers
  • Views 1166 views
  • Users 0 members are here
Options
Related 

        

            Post
             Go back to editing
        

    

    


    

    









		


















	
	
			
	
			
		
	
	
		

	    
	    
	    		
AD9174的204B建链但无波形输出问题

		
	
				

			

									
					    DaMingZ
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Oct 26, 2023 
				
			
			
		

		
		                     
				
        		

		    
		    		    
		    			

			    
工程的配置如下所示：


JESD204B模式：采用模式11；


JESD204B的Line数量：使用了8个line（前4个为I、后4个为Q）；


JESD204B数据率：数据率为2.6GSPS（I/Q）；


全链路内插值：通道旁路（内插1）、主通道内插4、主通道NCO设置为50MHz


ADC速率：10.4GSPS


参考时钟：325MHz


SYSREF：20.3125MHz


锁相环配置：使能PLL，N=8，M=2




在当前配置下，输入了1个5MHz的正弦波（格式已按照手册格式排好），应该输出一个55MHz的正弦波，但实际无输出，此时204B已经建链，且FPGA已观测到数据输出到204B端口；当修改为NCO Only模式时，则能够输出50MHz的正弦波，不知在参数配置方面是不是哪里配错了，下面是在正常输入下的参数配置步骤，希望得到大家的指点：







 /*
 * AD9174 config sequence.
 */
 //config Power-Up and Required Register-----------------------------reg_addr[0]-reg_addr[5];
 USpi_SigleReg_Write(BaseAddress,0x0000,0x0081);
 USpi_SigleReg_Write(BaseAddress,0x0000,0x003C);
 USpi_SigleReg_Write(BaseAddress,0x0091,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0206,0x0001);
 USpi_SigleReg_Write(BaseAddress,0x0705,0x0001);
 USpi_SigleReg_Write(BaseAddress,0x0090,0x0000);
 //DAC PLL Configuration---------------------------------------------reg_addr[6]-reg_addr[21];
 USpi_SigleReg_Write(BaseAddress,0x0095,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0790,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0791,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0796,0x00E5);
 USpi_SigleReg_Write(BaseAddress,0x07A0,0x00BC);
 USpi_SigleReg_Write(BaseAddress,0x0794,0x0008);
 USpi_SigleReg_Write(BaseAddress,0x0797,0x0010);
 USpi_SigleReg_Write(BaseAddress,0x0797,0x0020);
 USpi_SigleReg_Write(BaseAddress,0x0798,0x0010);
 USpi_SigleReg_Write(BaseAddress,0x07A2,0x007F);
 usleep(100000); //wait for 100ms
 USpi_SigleReg_Write(BaseAddress,0x0799,0x00C8);
 USpi_SigleReg_Write(BaseAddress,0x0793,0x0019);
 USpi_SigleReg_Write(BaseAddress,0x0094,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0792,0x0002);
 USpi_SigleReg_Write(BaseAddress,0x0792,0x0000);
 usleep(100000); //wait for 100ms
 reg_rd_buffer = USpi_Reg_Read(BaseAddress,0x07B5); //read AD7414 Register
 reg_rd_buffer = reg_rd_buffer & 0x0001;
 if(reg_rd_buffer == 0x0001)
 xil_printf("AD9714 PLL is locked\r\n");
 else
 xil_printf("AD9714 PLL is not lock\r\n");
 usleep(1000);
 
 //Delay Lock Loop (DLL) Configuration-------------------------------reg_addr[22]-reg_addr[30];
 USpi_SigleReg_Write(BaseAddress,0x00C0,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x00C0,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x00DB,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x00DB,0x0001);
 USpi_SigleReg_Write(BaseAddress,0x00DB,0x0000); 
 USpi_SigleReg_Write(BaseAddress,0x00C1,0x0068);
 USpi_SigleReg_Write(BaseAddress,0x00C1,0x0069);
 USpi_SigleReg_Write(BaseAddress,0x00C7,0x0001);
 reg_rd_buffer = USpi_Reg_Read(BaseAddress,0x00C3); //read AD7414 Register
 reg_rd_buffer = reg_rd_buffer & 0x0001;
 if(reg_rd_buffer == 0x0001)
 xil_printf("AD9714 DLL is locked\r\n");
 else
 xil_printf("AD9714 DLL is not lock\r\n");
 usleep(1000);
 
 //Calibration-------------------------------------------------------reg_addr[31]-reg_addr[36];
 USpi_SigleReg_Write(BaseAddress,0x0050,0x002A); 
 USpi_SigleReg_Write(BaseAddress,0x0061,0x0068);
 USpi_SigleReg_Write(BaseAddress,0x0051,0x0082);
 USpi_SigleReg_Write(BaseAddress,0x0051,0x0083);
 usleep(10000); //wait for 100ms
 reg_rd_buffer = USpi_Reg_Read(BaseAddress,0x0052); //read AD7414 Register
 xil_printf("AD9714 register 0x052 is:0x%x \r\n",reg_rd_buffer);
 USpi_SigleReg_Write(BaseAddress,0x0081,0x0003);
 usleep(1000);
 
 //JESD204B Mode Setup-----------------------------------------------reg_addr[37]-reg_addr[46];
 USpi_SigleReg_Write(BaseAddress,0x0100,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0110,0x000B); //single-link mode
 reg_rd_buffer = USpi_Reg_Read(BaseAddress,0x0110); //read AD7414 Register
 xil_printf("AD9714 register 0x110 is:0x%x \r\n",reg_rd_buffer);
 USpi_SigleReg_Write(BaseAddress,0x0111,0x0041); //Interp_Mode
 reg_rd_buffer = USpi_Reg_Read(BaseAddress,0x0110); //read AD7414 Register
 xil_printf("AD9714 register 0x110 is:0x%x \r\n",reg_rd_buffer);
 USpi_SigleReg_Write(BaseAddress,0x0084,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0312,0x0010); 
 USpi_SigleReg_Write(BaseAddress,0x0300,0x0001);
 USpi_SigleReg_Write(BaseAddress,0x0475,0x0009);
 USpi_SigleReg_Write(BaseAddress,0x0453,0x0007);
 USpi_SigleReg_Write(BaseAddress,0x0458,0x002F); 
 USpi_SigleReg_Write(BaseAddress,0x0475,0x0001);
 
 //Main DAC Datapath Setup: PA Protect and Main NCOs-----------------reg_addr[47]-reg_addr[74];
USpi_SigleReg_Write(BaseAddress,0x0008,0x00C0); //0x00C1.
 USpi_SigleReg_Write(BaseAddress,0x0112,0x0008); //complex mode 3B 0x0079 //0x0008
 USpi_SigleReg_Write(BaseAddress,0x0114,0x0013);
 USpi_SigleReg_Write(BaseAddress,0x0115,0x003B);
 USpi_SigleReg_Write(BaseAddress,0x0116,0x00B1); 
 USpi_SigleReg_Write(BaseAddress,0x0117,0x0013);
 USpi_SigleReg_Write(BaseAddress,0x0118,0x003B);
 USpi_SigleReg_Write(BaseAddress,0x0119,0x0001);
 USpi_SigleReg_Write(BaseAddress,0x011C,0x0000); 
 USpi_SigleReg_Write(BaseAddress,0x011D,0x0000);
 
 USpi_SigleReg_Write(BaseAddress,0x0113,0x0001);
 //JESD204B SERDES Required Interface Setup--------------------------reg_addr[75]-reg_addr[114];
 USpi_SigleReg_Write(BaseAddress,0x0240,0x00AA); 
 USpi_SigleReg_Write(BaseAddress,0x0241,0x00AA);
 USpi_SigleReg_Write(BaseAddress,0x0242,0x0055);
 USpi_SigleReg_Write(BaseAddress,0x0243,0x0055);
 USpi_SigleReg_Write(BaseAddress,0x0244,0x001F); 
 USpi_SigleReg_Write(BaseAddress,0x0245,0x001F);
 USpi_SigleReg_Write(BaseAddress,0x0246,0x001F);
 USpi_SigleReg_Write(BaseAddress,0x0247,0x001F);
 USpi_SigleReg_Write(BaseAddress,0x0248,0x001F); 
 USpi_SigleReg_Write(BaseAddress,0x0249,0x001F);
 USpi_SigleReg_Write(BaseAddress,0x024A,0x001F); 
 USpi_SigleReg_Write(BaseAddress,0x024B,0x001F);
 USpi_SigleReg_Write(BaseAddress,0x0201,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0203,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0253,0x0001); 
 USpi_SigleReg_Write(BaseAddress,0x0254,0x0001);
 USpi_SigleReg_Write(BaseAddress,0x0210,0x0016);
 USpi_SigleReg_Write(BaseAddress,0x0216,0x0005);
 USpi_SigleReg_Write(BaseAddress,0x0212,0x00FF); 
 USpi_SigleReg_Write(BaseAddress,0x0212,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0210,0x0087); 
 USpi_SigleReg_Write(BaseAddress,0x0216,0x0011);
 USpi_SigleReg_Write(BaseAddress,0x0213,0x0001);
 USpi_SigleReg_Write(BaseAddress,0x0213,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0200,0x0000); 
 
 usleep(1000000); //wait for 100ms
 USpi_SigleReg_Write(BaseAddress,0x0210,0x0086); 
 USpi_SigleReg_Write(BaseAddress,0x0216,0x0040);
 USpi_SigleReg_Write(BaseAddress,0x0213,0x0001);
 USpi_SigleReg_Write(BaseAddress,0x0213,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0210,0x0086); 
 USpi_SigleReg_Write(BaseAddress,0x0216,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0213,0x0001); 
 USpi_SigleReg_Write(BaseAddress,0x0213,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0210,0x0087);
 USpi_SigleReg_Write(BaseAddress,0x0216,0x0001);
 USpi_SigleReg_Write(BaseAddress,0x0213,0x0001); 
 USpi_SigleReg_Write(BaseAddress,0x0213,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0280,0x0005);
 USpi_SigleReg_Write(BaseAddress,0x0280,0x0001);
 usleep(100000); //wait for 100ms
 reg_rd_buffer = USpi_Reg_Read(BaseAddress,0x0281); //read AD7414 Register
 xil_printf("AD9714 register 0x281 is:0x%x \r\n",reg_rd_buffer);
 
 //Transport Layer Setup, Synchronization, and Enable Links----------reg_addr[115]-reg_addr[125];
 USpi_SigleReg_Write(BaseAddress,0x0308,0x0008); 
 USpi_SigleReg_Write(BaseAddress,0x0309,0x001A);
 USpi_SigleReg_Write(BaseAddress,0x030A,0x002C); 
 USpi_SigleReg_Write(BaseAddress,0x030B,0x003E);
 USpi_SigleReg_Write(BaseAddress,0x0306,0x000C);
 USpi_SigleReg_Write(BaseAddress,0x0307,0x000C);
 USpi_SigleReg_Write(BaseAddress,0x0304,0x000C); //LMFCDel
 USpi_SigleReg_Write(BaseAddress,0x0305,0x000C); //LMFCVar
 USpi_SigleReg_Write(BaseAddress,0x003B,0x00F1);
 USpi_SigleReg_Write(BaseAddress,0x003A,0x0002);
 usleep(100000); //wait for 100ms
 USpi_SigleReg_Write(BaseAddress,0x0300,0x0001);
 
 //Cleanup Registers-------------------------------------------------reg_addr[126]-reg_addr[127];
 //USpi_SigleReg_Write(BaseAddress,0x0085,0x0013);
 //USpi_SigleReg_Write(BaseAddress,0x01DE,0x0000);
 USpi_SigleReg_Write(BaseAddress,0x0008,0x00C0);
 USpi_SigleReg_Write(BaseAddress,0x0596,0x000C);









			

			
									
		                             
                        

    

                                            
                 Standard High Speed D/A Converters
                
                                                    
                 Digital Temperature Sensors
                
                                                    
                 ad9714
                
                                                    
                 ad7414
                
                                                    
                 High Speed D/A Converters =30MSPS
                
                                        
                                            
                
                
                                        
                                            
                
                
                                
                    Show More
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

  • 
	
    



	
			
		
	



    
	
    
		
    
							
					
    
		
    
		    
		    		    
			
				
									
							        
			
			
			
    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Oct 29, 2023 9:31 PM
            
            
						
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hello, 
    

    Pls confirm the TXEN pins are correctly configured. 
    

      
    

    if Txen is correct. Pls try to adjust the LMFCDel, LMFCVar registers from the part.  See the "Link Delay " section of the datasheet.
    

    

    Regards
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

    • 

	

  • 
	
    



	
		
	
	



    
	
    
		
    
							
					
    
		
    
		    
		    		    
			
				
									
							        
			
			
			
            
						
                            
            
            				
            
                on Oct 30, 2023 6:51 AM
            
            
												
						in reply to ADIApproved
					
										
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Thank you for your reply
    1.TXEN is always assigned high;
    2.I think ‘Link Delay’ is used to eliminate the delay inconsistency between multiple links, including LMFCDel and LMFCVar. However, Mode 11 of JESD204B is Single Link Mode, and there is no alignment problem between multiple links. The different settings of the delay parameter will only lead to the change of the waveform output moment, and will not cause no waveform output, right?
    3. I am reading the link delay chapter carefully, and at the same time tried several sets of parameter configurations of LFMCDel and LMFCVar, the result is no change, still no waveform output.
    

    Looking forward to your reply and guidance, thank you very much!
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

    • 

	

  • 
	
    



	
		
	
	



    
	
    
		
    
							
					
    
		
    
		    
		    		    
			
				
									
							        
			
			
			
            
						
                            
            
            				
            
                on Oct 30, 2023 6:51 AM
            
            
												
						in reply to ADIApproved
					
										
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Thank you for your reply
    1.TXEN is always assigned high;
    2.I think ‘Link Delay’ is used to eliminate the delay inconsistency between multiple links, including LMFCDel and LMFCVar. However, Mode 11 of JESD204B is Single Link Mode, and there is no alignment problem between multiple links. The different settings of the delay parameter will only lead to the change of the waveform output moment, and will not cause no waveform output, right?
    3. I am reading the link delay chapter carefully, and at the same time tried several sets of parameter configurations of LFMCDel and LMFCVar, the result is no change, still no waveform output.
    

    Looking forward to your reply and guidance, thank you very much!
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

    • 

	

  • 
	
    



	
		
	
	



    
	
    
		
    
							
					
    
		
    
		    
		    		    
			
				
									
							        
			
			
			
    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Oct 30, 2023 11:53 PM
            
            
												
						in reply to DaMingZ
					
										
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi , 
    

    For single link, the Link Delay needs to be correctly set.
    

    regards 
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

    •