1."In dual-port mode, the data must be delivered at the sample rate (up to 250 MSPS). In single-port mode, data must be delivered at twice the sample rate. Because the data inputs function only up to 250 MSPS, it is only practical to operate the DAC clock at up to 125 MHz in single-port mode."--《Rev. B | Page 25 of 30》
Dose it means ： DAC Clock(CLKP,CLKN) frequency is a maximum of 125 MHz in single-port mode , and the DCO keep the same ?
2."In single-port mode, data must be delivered at twice the sample rate ." --《Rev. B | Page 25 of 30》
Dose it means ： the data transmission frequency is a maximum of 250 MHz when the DAC Clock(CLKP,CLKN) frequency is a maximum of 125 MHz in single-port mode ? or the data transmission frequency is a maximum of 125 MHz when the DAC Clock(CLKP,CLKN) frequency is a maximum of 125 MHz in single-port mode , but both the edges of the clock (CLKP,CLKN) are used to capture the data from the FPGA logic at twice the throughput (DDR mode)?
Looking forward to your help , thanks!!
