You can set the interpolation rate to 4x by setting register address 0x01 bits [7:6] to 10. Please refer to page 36 of the datasheet for more details on 4x interpolation and pages 18-21 for the SPI register map.
What configuration are you using? CLKIN can function either as input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled).
If CLKIN is configured as input data rate then DAC data rate clock = input data rate * interpolation.
If CLKIN is configured as DAC Data rate clock then input data rate = DAC data rate clock / Interpolation.
In your example, I assume 25MHz is the data rate. the DAC data rate clock would be multiplied by interpolation (4x) = 100MHz. Your 25MHz input data would be sampled by the 100MHz DAC clock. Please refer to page 27 - 32 of the datasheet for more details. Hope this helps.
What configuration are you using? CLKIN can function either as input data rate clock (PLL enabled) or as a DAC data rate clock (PLL disabled).
If CLKIN is configured as input data rate then DAC data rate clock = input data rate * interpolation.
If CLKIN is configured as DAC Data rate clock then input data rate = DAC data rate clock / Interpolation.
In your example, I assume 25MHz is the data rate. the DAC data rate clock would be multiplied by interpolation (4x) = 100MHz. Your 25MHz input data would be sampled by the 100MHz DAC clock. Please refer to page 27 - 32 of the datasheet for more details. Hope this helps.
