I use Xilinx's FPGA to connect to ad9172.
The input data of my DAC is DDS, jesd can be synchronized, and DA can work normally.
However, the data after DDR cache collected and processed by ad can not be synchronized with the jesd of DA.
This part of the data is correct after being processed by ILA and MATLAB,
Only by changing the input data, the synchronization of jesd link is pulled down