we need to know the CPOL level of ad7292, but puzzled by the datasheet of EN rev.A and Chinese edition rev.0, due to them don't identity.
.......this is cited from EN rev.A, and there have two dash line pulses of SCLK in CS in disactive state, what mean of them?
...this is cited form CN rev.0, and it is not same as en one, especially in the t8 cs disactive phase, cn datasheet using solid line mark it as high leve, if this is ture, we think that the CPOL is HIGH, nevertheless, what means for the dash line pulse?
long for the ADI expert give some hint for it.
CQUPT: GUOPING CHEN
11th, Nov., 2020
1. dash line means don't care! It can be high or low.
2. Rev. A is newer than Rev. 0. Please refer to Rev.A.
3. CPOL=0 &CPAL=1 mode should be fine for fSCLK <=15MHz for most MCU。For faster SCLK, please…
3. CPOL=0 &CPAL=1 mode should be fine for fSCLK <=15MHz for most MCU。For faster SCLK, please check the specific timing.