Refer to

Currently my design intention with FPGA is using below modes and selection:

  • Continuous mode at SPI read, CRC disabled
  • DATA_STAT enabling with reading back the appended data to DATAOUT at continuous read-back(this 8-bit status will be utilized to identify the channel information with converted data).
    • This is very important, I will use channel data appended at this to identify converted data belongs to which channel.
  • ODR set at 250 kSPS
  • Using internal oscillator and internal reference.
  • Channel 0 configuration : AIN0(+ve analog input) and AIN1(-ve analog input)
  • Channel 1 configuration : AIN2(+ve analog input) and AIN3(-ve analog input)
  • Channel 2 and 3 disabled.


  • How many additional clocks need to clock into the chip with DATA_STAT enabled? If configured 24-bit I will clock 24-bit to read-back from Data Register(0x04), else 16-bit.
  • Which byte represents data from Status Register?

 Issue I am facing,

  • DATAOUT went high ‘1’ after one cycle read-back at continuous conversion mode.
  • If there are 250kSPS occurred at DOUT, which observable at DOUT adjacent High period, there were no data retrieved out even there were conversion happened.