2. After the master has addressed the AD7991/AD7995/AD7999, the part begins to power up on the ninth SCLK rising edge. At the same time, the acquisition phase begins. When approximately 0.6 µs have elapsed, the acquisition phase ends. The input is sampled and a conversion begins.
On the ninth SCLK rising edge of the second byte, if the master sends an ACK, it keeps reading conversion results and the AD7991/AD7995/AD7999 powers up and performs a second conversion.
2. After the master has addressed the AD7991/AD7995/AD7999, the part begins to power up on the ninth SCLK rising edge. At the same time, the acquisition phase begins. When approximately 0.6 µs have elapsed, the acquisition phase ends. The input is sampled and a conversion begins.
On the ninth SCLK rising edge of the second byte, if the master sends an ACK, it keeps reading conversion results and the AD7991/AD7995/AD7999 powers up and performs a second conversion.
