在使用AD9251-40 做FPGA 控制采集时候发现由ADC采集上来的信号有非常大的串扰，怀疑是ADC差分时钟的问题。所用FPGA 型号是EP4CE40F23I7, 采用方式是直接用FPGA IO 口产生LVDS差分时钟输出给ADC，请问一下各位高手这里是否会出问题
现在时钟频率是20M
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