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AD9528 output jitter problem

Hello,

I am using the AD9528 to generate a 100Mhz clock for the ADC sampling clock. When the AD9528 outputs only one line, I use the phase noise meter to test the output 100Mhz jitter is 270fs, and when the output is fully turned on, the 100Mhz clock jitter becomes 320fs. The result of the ADISIMPLL simulation should be 167fs.


Question 1: Even for single-channel output LVDS, why is the jitter is 270fs but not 167fs? Although 167fs is a theoretical value, I want to exclude test reasons and circuit design differences, at least there should be 200fs. May I ask what causes it to deteriorate?

Question 2: Why does jitter get worse when the output is all open?

I used the LT8643S+ADP7159ARDZ to power the VCXO and AD9528, The power ripple is very small, below 2mV
The following diagram shows the design Settings. Thank you!

  • The phase noise of the phase-locked loop system mainly comes from the input reference source, phase detector, charge pump, loop filter and voltage-controlled oscillator (VCO), so there must be a problem in the circuit design, which leads to further deterioration of the phase noise. There are several measures to effectively reduce jitter:


    1: Select a low phase noise reference clock source to improve the system phase noise.
    2: Maximize the phase detector frequency, that is, increasing the frequency of the phase detector can effectively reduce the system phase noise.
    3: Using a high-order loop filter and reducing the bandwidth of the loop filter can effectively improve the phase noise performance.
    4: Make full use of the cascaded phase-locked loop architecture of AD9528, and the VCXO must also have low phase noise performance.


    If all outputs are turned on, be sure to terminate the 50Ω load to avoid full reflection due to no load, which will affect the internal circuit. I suggest that you first perform performance testing and evaluation on the ADI official evaluation board before designing the circuit.