Hello,
I am using the AD9528 to generate a 100Mhz clock for the ADC sampling clock. When the AD9528 outputs only one line, I use the phase noise meter to test the output 100Mhz jitter is 270fs, and when the output is fully turned on, the 100Mhz clock jitter becomes 320fs. The result of the ADISIMPLL simulation should be 167fs.
Question 1: Even for single-channel output LVDS, why is the jitter is 270fs but not 167fs? Although 167fs is a theoretical value, I want to exclude test reasons and circuit design differences, at least there should be 200fs. May I ask what causes it to deteriorate?
Question 2: Why does jitter get worse when the output is all open?
I used the LT8643S+ADP7159ARDZ to power the VCXO and AD9528, The power ripple is very small, below 2mV
The following diagram shows the design Settings. Thank you!