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PLL是否可以优化输入时钟

		
	
				

			

									
					    caodeminchina
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Dec 25, 2024 
				
			
			
		

		
		                     
				
        		

		    
		    		    

		      		            		        
Category: Hardware

    		        		            		    
Product Number:  PLL 

    		        		    		    

		    		    
		    			

			    
使用ADF4001中的截图方式，输入13MHz的相位噪声比较差，VCXO的相位噪声很好，此时的输出是否跟VCXO的差不多？相当于优化了输入时钟的相位噪声？ 


如果输出相位噪声跟输入差不多，那有什么方法可以优化呢？

			

			
									
		                                 
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