ADF4159 NEG_BLEED_EN 配置问题，以及DIGITAL_LOCK_DETECT检测不锁定

Thread Summary

The user is troubleshooting issues with a PLL configuration using a 50 MHz reference clock and a 24 GHz VCO. When R3_DB21 is enabled, the CP voltage is stable at 1.4V and the VCO output is stable at 24 GHz. Disabling R3_DB21 causes the CP voltage to fluctuate. The digital lock detect (LDP) is not working even when the CP voltage is stable and R3[7] is set to 1. The support engineer suggested checking the impact of negative bleed current and ensuring the LDP bit is set, but the issue persists.
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