what is max bandwidth of ad9361 RX and TX channel，whether 2*2mimo ,the max bandwidth of channel (RX or TX ) change or not?

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I find a tab from a document <AD9361_Reference_Manual_UG-570.pdf> , I'm confused. Why is 1T1R twice as fast as 2T2R（max data rate (combined I and Q words)）???

At UG-570 page 92, just above the Table 48, write:"The maximum DATA_CLK rate is limited to 61.44 MHz, so the data rates are limited by this factor and the 56 MHz maximum analog filter bandwidth". So at CMOS interface, the data rate is limited by DATA_CLK rate

At UG-570 page 92, just above the Table 48, write:"The maximum DATA_CLK rate is limited to 61.44 MHz, so the data rates are limited by this factor and the 56 MHz maximum analog filter bandwidth". So at CMOS interface, the data rate is limited by DATA_CLK rate