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Why AD9364 double the bandwidth of TX data?

Hi,my board is a 5.8GHz transmitor made up of a FPGA +AD9364.

The FPGA has modulated  the baseband data and put it to 8MHz intermidiate frequency.

The band width is 6.875MHz,and the sample rate is 55MHz.The data is sent to AD9364 through lvds interface with 110MHz speed.

I set the TFIR as 2x speed and enabled the FIR filter,and set THB3 as 3x.,so the DAC speed is 330MHz which gives a 6 times ratio to the sample rate.

I have made a 96 taps FIR filter with MATLAB,and filled the coefficients into the memory.

Then I see  the analog bandwidth is not 6.875MHz, but is doubled as 13.75MHz.

Can some one help me to find out what's wrong with my settings?