AD9364 TX_VCO_LDO_OUT and RX_VCO_LDO_OUT give 0V out and BBPLL calibration always fail


     I just have 3 FPGA boards and 3 custom AD9364 boards designed by myself. When I configured AD9364 boards with FPGA boards in SPI commands as attached below,the BBPLL calibration can never get "1" at bit 7 of register 0x05E. The BBPLL words are the same as writen when I read them back,and the values I read from  register 0x017,0x050, 0x051 are all 0x00.

I can find that the TX_VCO_LDO_OUT and RX_VCO_LDO_OUT give out 0V voltage while the 1.3V voltages are all good when I checked all 3 AD9364 boards. The ENABLE/TXNRX/EN_AGC/RESETB are all floating as I remove the FPGA board when check the voltages of AD9364 boards.

I think that the LDO_OUT voltages should be 1.1V when there is a good 1.3V. If the 1.1V is not good ,the calibration cann't go through.

Hope some one can help me with this issue,thanks!


BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz
SPIWrite 3DF,01 // Required for proper operation
SPIWrite 2A6,0E // Enable Master Bias
SPIWrite 2A8,0E // Set Bandgap Trim
REFCLK_Scale 40.000000,1,2 // Sets local variables in script engine, user can ignore
SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 009,17 // Enable Clocks
WAIT 20 // waits 20 ms
// Set BBPLL Frequency: 1320.000000
SPIWrite 045,00 // Set BBPLL reflclk scale to REFCLK /1
SPIWrite 046,05 // Set BBPLL Loop Filter Charge Pump current
SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1
SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1
SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2
SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy
SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy
SPIWrite 043,00 // BBPLL Freq Word (Fractional[7:0])
SPIWrite 042,00 // BBPLL Freq Word (Fractional[15:8])
SPIWrite 041,00 // BBPLL Freq Word (Fractional[23:16])
SPIWrite 044,21 // BBPLL Freq Word (Integer[7:0])
SPIWrite 03F,05 // Start BBPLL Calibration
SPIWrite 03F,01 // Clear BBPLL start calibration bit
SPIWrite 04C,86 // Increase BBPLL KV and phase margin
SPIWrite 04D,01 // Increase BBPLL KV and phase margin
SPIWrite 04D,05 // Increase BBPLL KV and phase margin
WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 345.600 us (Done when 0x05E[7]==1)

SPIRead 05E // Check BBPLL locked status  (0x05E[7]==1 is locked)

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