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AD9361 LVDS模式下DATA_CLK输入至FPGA后，FPGA PLL无法锁定



		

			

									
					    MoQQ
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on May 11, 2020 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    AD9361配置为2R2T-LVDS模式，全双工，接收和发送波形均正常，但是FPGA 内部的PLL时常失锁，通过调节0x006和0x007寄存器好像有影响，调节LVDS模式bias好像也有影响
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 ad9361
                
                                                    
                 Wideband Transceiver IC
                
                                                    
                 RF Integrated Transceivers