Suggested Answer

AD9361接收本振锁定问题 0

69 views

1 reply

on 8 Apr 2021 by 君临天下
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AD9361 读取RSSI的symbol需要怎么转换？ 0

136 views

5 replies
on 31 Mar 2021
by Admin_ADI
Suggested Answer

iio oscilloscope and zedboard 0

37 views

1 reply
on 30 Mar 2021
by shawn
Suggested Answer

Filter setting 0

156 views

3 replies
on 11 Dec 2020
by shawn
Answered

AD9361发射幅度不一致问题 0

543 views

5 replies

on 20 Nov 2020 by 求知222
Suggested Answer

关于ADRV9364-z7020与matlab中Communications Toolbox Support Package for Xilinx Zynq-Based Radio 硬件支持包进行Host Machine Checklist时出错 0

253 views

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on 4 Nov 2020 by CLi285
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193 views

1 reply
on 3 Nov 2020
by shawn
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175 views

1 reply
on 20 Oct 2020
by shawn
Not Answered

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165 views

0 replies

on 20 Oct 2020 by 1135553530@qq.com
Suggested Answer

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259 views

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on 16 Oct 2020 by liangjun1972
Not Answered

AD9361 LVDS模式下DATA_CLK输入至FPGA后，FPGA PLL无法锁定 0

327 views

1 reply
on 14 May 2020
by shawn
Suggested Answer

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301 views

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on 13 May 2020
by shawn
Suggested Answer

AD9371 I/Q不平衡 +1

374 views

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on 13 May 2020
by shawn
Answered

关于如何更改AD9361基带波形 +1

313 views

1 reply
on 13 May 2020
by shawn
Answered

射频地与数字地都可以不用分割的吗？ +1

215 views

1 reply
on 17 Apr 2020
by shawn
Suggested Answer

AD9361采用40M有源晶振从XTALN引脚输入，XTALP引脚悬空,输出信号解码有问题，在XTALP-XTALN之间接入40M无源晶体就没问题，请教下大家怎么解决问题 0

610 views

1 reply
on 16 Apr 2020
by shawn
Answered

No-OS中ad9361_tx_bb_second_filter_calib函数是不是有错误？ +1

220 views

1 reply
on 16 Apr 2020
by shawn
Answered

ad9361 bist测试 +1

485 views

1 reply
on 15 Apr 2020
by shawn
Not Answered

购买咨询 0

199 views

1 reply
on 8 Apr 2020
by ternence
Answered

AD9361的初始化校准 +1

398 views

1 reply
on 12 Mar 2020
by shawn