I’m reviewing the MAX30009 EVB layout and noticed an aggressive copper removal strategy in the inner layers.
From Layer 2 onward, copper is only kept near the input area. Layer 3 has even larger clearances, and on Layer 4 there is almost no copper pour at all except for signal routing, creating a large multi-layer cutout region.
From a mixed-signal / low-level analog perspective, removing reference planes usually hurts return paths and noise immunity, so I’m curious about the design intent here.
Is this mainly to reduce parasitic capacitance, leakage, or substrate coupling at the bioimpedance inputs? Or is this EVB layout optimized for characterization rather than production?
Which parts of this approach are critical to preserve, and which could be relaxed in a custom design?
