ADAU1777 DAC to ADC loop delay

As shown in Figure 1, use the EVAL-ADAU1777Z development board to test the DAC to ADC loop delay. Use the I2S interface of the external MCU to send the superimposed sine data (600Hz+3kHz), which is played by the speaker connected to J21 (DIFF_OUT_L), and the data is collected and saved through the ECM connected to J8 (AIN0). By comparing the data of DAC and ADC in Figure 2, I found that the loop delay has 30 sampling periods (the sampling rate is 192kHz). my question is:
1. For the EVAL-ADAU1777Z development board, I only need its DAC and ACD data to be transmitted through I2S without processing. Is there a problem with the settings of my SigmaStudio project?
2. In theory, under this test condition (external MCU+I2S), what is the lowest delay of the DAC to ADC loop? What should i do?
3. If the input PGA of the ADC is turned on, will it increase the loop delay? Is there a way to avoid introducing too much loop delay while amplifying the ADC input.