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AD1933 default standlone timing operation

我们产品中准备采用AD1933,8路DAC。根据手册有一些疑惑。

所有的寄存器都采用复位后的默认设置。MCLK是12.288Mhz。

1,relation of MCLK BCLK  LRCLK

     after reset, BCLK s is 64 per frame, so BCLK = MCLK/4 = 3.072Mhz,LRCLK = BCLK / 64 = 48K 。

     Is it correct?

2,default Word Length is 24bit,but LRCLK = BCLK / 64,when LRCLK is high or low,the word length is 32bit 。 

     so, when Word Length is 24bit,the lower 8 bits is NULL?

3,according to datasheet, we use I2S timing, but nothing output 。

     MCLK In is 12.288,AD1933 MCLK Out is 12.288 too,。and use MCLK Out divide LRCLK BCLK,but no output at all。

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