AD1933 default standlone timing operation

我们产品中准备采用AD1933,8路DAC。根据手册有一些疑惑。

所有的寄存器都采用复位后的默认设置。MCLK是12.288Mhz。

1,relation of MCLK BCLK  LRCLK

     after reset, BCLK s is 64 per frame, so BCLK = MCLK/4 = 3.072Mhz,LRCLK = BCLK / 64 = 48K 。

     Is it correct?

2,default Word Length is 24bit,but LRCLK = BCLK / 64,when LRCLK is high or low,the word length is 32bit 。 

     so, when Word Length is 24bit,the lower 8 bits is NULL?

3,according to datasheet, we use I2S timing, but nothing output 。

     MCLK In is 12.288,AD1933 MCLK Out is 12.288 too,。and use MCLK Out divide LRCLK BCLK,but no output at all。

Parents
  • +1
    •  Analog Employees 
    on Nov 25, 2019 9:11 PM

    Hello hitecor,

    I see you posted this twice, once only in Chinese and this one with some English. I will repeat my response here as well. 

    I received notification of this post because you wrote the part number in the post. So I see this is on the Chinese EngineerZone site. I apologize for answering in English. I am the support person for the AD1933. 

    1) Those frequencies are correct.

    2) The 8 extra bits past the 24 bits are internally truncated. It does not matter what the data is for those bits. They will be ignored. 

    3) If I understood your questions correctly.

    The LRCLK and BCLK must come from the device that is sending the data. You cannot divide it down from the MCLK output. I suppose as a test it might work but there is no point in doing that. You can always set the LRCLK and BCLK pins to be a Master. These control bits are located in the DAC Control 1 register. Then internally they will divide down the master clock and send them out of the pins. 

    PLL and Clock Control 0 register, bit 7, must be changed to be a "1" to enable the part. 

    All the registers in this part default to a value of 0.

    The data in your screenshot shows the sign bit aligned with the edge of the LRCLK. So therefore, you will need to change DAC Control 0 register bits 5:3 to have the value of 0b001. This is for no delay in the serial data. 

    I think those few changes should help you get further. 

    Dave T

Reply
  • +1
    •  Analog Employees 
    on Nov 25, 2019 9:11 PM

    Hello hitecor,

    I see you posted this twice, once only in Chinese and this one with some English. I will repeat my response here as well. 

    I received notification of this post because you wrote the part number in the post. So I see this is on the Chinese EngineerZone site. I apologize for answering in English. I am the support person for the AD1933. 

    1) Those frequencies are correct.

    2) The 8 extra bits past the 24 bits are internally truncated. It does not matter what the data is for those bits. They will be ignored. 

    3) If I understood your questions correctly.

    The LRCLK and BCLK must come from the device that is sending the data. You cannot divide it down from the MCLK output. I suppose as a test it might work but there is no point in doing that. You can always set the LRCLK and BCLK pins to be a Master. These control bits are located in the DAC Control 1 register. Then internally they will divide down the master clock and send them out of the pins. 

    PLL and Clock Control 0 register, bit 7, must be changed to be a "1" to enable the part. 

    All the registers in this part default to a value of 0.

    The data in your screenshot shows the sign bit aligned with the edge of the LRCLK. So therefore, you will need to change DAC Control 0 register bits 5:3 to have the value of 0b001. This is for no delay in the serial data. 

    I think those few changes should help you get further. 

    Dave T

Children