AD1933 default standlone timing operation

Hello hitecor,

I see you posted this twice, once only in Chinese and this one with some English. I will repeat my response here as well. 

I received notification of this post because you wrote the part number in the post. So I see this is on the Chinese EngineerZone site. I apologize for answering in English. I am the support person for the AD1933. 

1) Those frequencies are correct.

2) The 8 extra bits past the 24 bits are internally truncated. It does not matter what the data is for those bits. They will be ignored. 

3) If I understood your questions correctly.

The LRCLK and BCLK must come from the device that is sending the data. You cannot divide it down from the MCLK output. I suppose as a test it might work but there is no point in doing that. You can always set the LRCLK and BCLK pins to be a Master. These control bits are located in the DAC Control 1 register. Then internally they will divide down the master clock and send them out of the pins. 

PLL and Clock Control 0 register, bit 7, must be changed to be a "1" to enable the part. 

All the registers in this part default to a value of 0.

The data in your screenshot shows the sign bit aligned with the edge of the LRCLK. So therefore, you will need to change DAC Control 0 register bits 5:3 to have the value of 0b001. This is for no delay in the serial data. 

I think those few changes should help you get further. 

Dave T

Hi Dave T

    Thanks for the help, we ignor the important register, PLL and Clock Control 0 register, bit 7, must be changed to be a "1" to enable the part. 

    Now this chip could run.

    Now their are some confusing questions:

    1, we are using cystal 12.288Mhz, so MCLK/IN and MCLK/OUT are the same 12.288.

        And then MCLK output to FPGA, and then FPGA use MCLK/OUT to generate BCLK and LRCLK. 

        Per your answer, should we use AD1933 to generate BCLK and LRCLK to FPGA, and FPGA act as slave on BCLK and LRCLK?

    2, the PLL locked is off, PLL and Control 1 bit 3 is still low. So could we just use MCLK to drive AD1933, set PLL and Control 1 register bit0 and bit 1 to 1?

    3, we need 192K sample rate. 

        A, set DAC Control 0 2:1 to 10, change sample rate.

        B, set BCLK 12.288Mhz, LRCLK 192KHz.

        Is the two steps enough?

     4, phase of MCLK and BCLK.

         In the datasheet, I could not find phase relation of MCLK and BCLK, only find phase of BCLK and LRCLK.

    Thank you for help again, and Merry Christmas!

Hello hitechor,

Thank you for the Christmas wishes. I had a great Holiday break and I hope you have a great Chinese New Year break coming up before too long! You have my well wishes in advance. 

You are asking several questions that are difficult to explain without using too many long English sentences. 

I am getting a better understanding of your design requirements. 

Since you would like to operate at 192kHz fs, I recommend you setup the part with the ADC as the master clocks for the system. Then operate the FPGA outputs to the DAC as a master. Here is a summary:

PLL input is from the crystal, 12.288MHz

ADC is set to use the internal clocks and outputs LRCLK = 192kHz and BLCK at 12.288MHz. So this is for an I2S signal. You will need to use both ASDATA outputs to use all four channels. 

FPGA data inputs will need to slave from the ADC clocks and you can use the BCLK split off for the FPGA to use as a master clock. 

FPGA data outputs will need to be a Master to send out LRCLK= 192kHz and BCLK = 12.288MHz to go to the DAC side of the codec.

DAC will be set to be a slave to the LRCLK and BCLK from the FPGA.

The DAC clock source for its Master clock can be the internal PLL since it is the same for the entire system. This is for PLL and Clock Control Register 1 bit 0 = 0. It defaults to this setting. 

I am recommending this arrangement of masters and slaves because you are running at 192kHz fs. At these clock and data speeds the timing margin for the data is very small and so the device that is sending the data is best to be a master so there is no delay for the data to change on the bit clock edge. You only have the time of flight and capacitance issues on the transmission line. 

Regarding your question #2:

You must use the PLL, if you use the MCLK input then the master clock will need to be 512 x fs at 48kHz or 24.576MHz. It is best to use the PLL. If it is not locking then you need to find out why? Check that the PLL Loop filter components are correct? Check that the crystal clock outputs look good. 

Regarding your other questions:

hitechor said:

3, we need 192K sample rate. 

        A, set DAC Control 0 2:1 to 10, change sample rate.

        B, set BCLK 12.288Mhz, LRCLK 192KHz.

        Is the two steps enough?

A: Yes.

B: Set the BCLK's per frame to 64. With 64 bit clocks per frame you will get 12.288MHz. (192kHz x 64) 

The DACs will default to slaves and to the BCLK source to be the DBCLK pin. So you should not have to change anything else... 

I just now remembered that you are using the AD1933 which is only DACs. However, all I said is still true. There are still the clocks that are normally the ADC clocks are used for the Auxiliary TDM ports and so you can still use that section to create clocks for the system. In this case you will only need to use the bit clock signal on Pin 28. 

Look at the Auxiliary TDM Control 1 register. bit 6 you will need to set to Master and that will give you a bitclock to use that is off of the internal PLL and is locked to the same clock as the DAC. Run your FPGA off of that clock. 

hitechor said:

4, phase of MCLK and BCLK.

         In the datasheet, I could not find phase relation of MCLK and BCLK, only find phase of BCLK and LRCLK.

This is because it is not important. The phase difference does not matter. What matters are the number of edges of the master clock verses the number of edges of the BCLK and LRCLK. There must be the correct number of master clock transitions per frame. They are counted and if it is not correct the DACs mute. This is why the BCLK and LRCLKs clocks must be derived from the same master clock. The phase is not important. 

Thanks,

Dave T