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AD8475仿真

按照CN0296仿真时,当在AD8475前面加上AD8065后,仿真没有输出,或者输出全为0;一直不知道是什么原因?

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  • 不知道

    我仿真了一下,应该是AD8475的spice模型有问题,我已经反馈了该模型的问题,估计需要一段时间才能解决。

  • 我们已经修正了这个模型,参考附件的cir文件,需要注意的是AD8065的正向输入的最大值到电源轨有2.4V的压差,这个会影响最终的仿真结果。参考下图的Datasheet中的截图:

    仿真结果如下:

    你可以发现输入的上限电压被钳位。

    * AD8475 SPICE Macro-model  
    * Description: Amplifier
    * Generic Desc: Differential input/output, G=0.8&0.4 High Speed Funnel Amp and ADC Driver
    * Developed by: ADI - LPG
    * 
    * Revision History:
    * A(10/2010) - LG (Original Rev)
    * B(03/2012) - PRB
    * C(06/2014) - SH (Updated to new header style. Bug fixes and performance improvements.)
    * D(04/2022) - IW (Bug fixes in LTspice)
    * Copyright 2010, 2014, 2022 by Analog Devices
    * 
    * Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
    * indicates your acceptance of the terms and provisions in the License Statement.
    *
    *
    * BEGIN Notes:
    *
    *
    * Not Modeled:
    *   Temperature effects
    *   Harmonic Distortion
    *   
    * Parameters modeled include:
    *   Supply current incl load
    *   Offset voltage
    *   PSRR vs frequency
    *   Output swing vs load
    *   Input Common-Mode Voltage Range
    *   Bandwidth
    *   Pulse Response variation with cap load
    *   Noise
    *   VOCM Bandwidth
    *   Slew rate
    *   Gain error and gain resistance
    *   
    * END Notes
    *
    * Node assignments
    *              inverting input 0.8x
    *              |       inverting input 0.4x
    *              |       |       Positive Supply
    *              |       |       |   Common Mode Input
    *              |       |       |   |    Positive Output
    *              |       |       |   |    |    Negative Output
    *              |       |       |   |    |    |    No Connect
    *              |       |       |   |    |    |    |  Negativesupply
    *              |       |       |   |    |    |    |  |   non_inverting input 0.4x
    *              |       |       |   |    |    |    |  |   |       non_inverting input 0.8x
    *              |       |       |   |    |    |    |  |   |       |
    .SUBCKT AD8475 -IN0.8X -IN0.4X +VS VOCM +OUT -OUT -VS +IN0.4X +IN0.8X
    *** GAIN RESISTORS AND INPUT CLAMPS ***
    R1 N004 +IN0.8X 1.25e3
    R2 N016 -IN0.8X 1.25e3
    R17 +IN0.8X +IN0.4X 1.25e3
    R18 -IN0.8X -IN0.4X 1.25e3
    VISENSE2 VX2 N131 0
    R14 N131 N016 1.00077741736e3
    VISENSE1 VX1 N130 0
    R15 N130 N004 1.00022262661e3
    
    DC1 N004 N110 DX
    V6 +VS N110 1.2
    DC2 N111 N004 DX
    V7 N111 -VS 0.4
    
    *** DIFFERENTIAL GAIN AND DOMINANT POLE ***
    G1 N013 N018 N004 N016 -.034349
    R16 N013 N018 1e9
    G3 0 VX1 VMID N013 .253192
    G4 0 VX2 VMID N018 .253192
    C1 N009 N013 3.2e-12
    C2 N023 N018 3.2e-12
    R19 VX1 N009 200
    R20 VX2 N023 200
    R11 VX1 0 1e9
    R12 0 VX2 1e9
    
    *** COMMON-MODE GAIN AND VOCM BW ***
    E5_VOCM_ERROR N032 VOCM VOCM 0 .2e-3
    R7 +VS N032 200e3
    R8 N032 -VS 200e3
    V3 N031 N032 -10e-6
    E1_balance N030 N031 +OUT -OUT 99.7927e-6
    R5 N015 VX2 1e6
    R6 VX1 N015 1e6
    G2 0 N018 N015 N030 .00015
    R9 N018 0 1e9
    C3 N018 0 1e-18
    G5 0 N013 N015 N030 .00015
    R10 N013 0 1e9
    C4 N013 0 1e-18
    
    *** NOISE ***
    V_Noise N001 0 0
    R13 N001 0 .0166
    DN1 N002 N001 DN
    VN1 0 N002 0.2
    H1_Noise -OUT N008 V_Noise -2.5
    H2_Noise +OUT N027 V_Noise 2.5
    
    
    *** CMRR SECTION ***
    R34 N040 0 2
    C11 N040 N039 1e-9
    R35 8 0 2
    C12 8 N041 1e-9
    E11 N039 0 N042 0 1
    R36 N040 N039 1000
    E12 N041 0 N040 0 1
    R37 8 N041 1000
    R38 N044 0 2
    C13 N044 N043 1e-9
    R39 6 0 2
    C14 6 N045 1e-9
    E13 N043 0 N042 0 1
    R40 N044 N043 1000
    E14 N045 0 N044 0 1
    R41 6 N045 1000
    E15 N012 N011 6 0 -8e-3
    E16 N026 N025 8 0 8e-3
    R42 +IN0.4X N042 1e6
    R43 N042 -IN0.4X 1e6
    R44 +IN0.8X N042 1e6
    R45 N042 -IN0.8X 1e6
    
    *** PSRR SECTION ***
    R23 N034 0 46
    C5 N034 N033 1e-9
    R27 4 0 46
    C8 4 N035 1e-9
    E4 N033 0 +VS -VS 1
    R21 N034 N033 1000
    E5 N035 0 N034 0 1
    R22 4 N035 1000
    R24 N037 0 46
    C6 N037 N036 1e-9
    R25 2 0 46
    C7 2 N038 1e-9
    E3 N036 0 +VS -VS 1
    R26 N037 N036 1000
    E6 N038 0 N037 0 1
    R28 2 N038 1000
    E7 N011 N010 2 0 -8.173e-3
    E8 N025 N024 4 0 8.173e-3
    
    *** REFERENCE AND SUPPLY CURRENT ***
    I1 +VS -VS 3.2e-3 ;3.2mA Iq
    GIsy +VS -VS VALUE={I(V_current_sense+)-I(V_current_sense-)}
    ;Fsup1 N100 0 POLY(4) V_Current_Sense+ V_Current_Sense- VISENSE1 VISENSE2 0 -1 -1 1 1
    ;Dsup1 +VS N101 DX
    ;DZsup1 N100 N101 DZ
    ;Dsup2 N102 -VS DX
    ;DZsup2 N102 N100 DZ
    
    EMID VMID 0 POLY(2) +VS 0 -VS 0 0 0.5 0.5
    EVP VP 0 +VS 0 1
    EVN 0 VN 0 -VS 1
    
    *** SLEW RATE ***
    G10 0 VZ1 VX1 VY1 1e-3
    RZ1 0 VZ1 1e9
    DSLEW1 VC1 0 DZ
    DSLEW2 VC1 VZ1 DZ
    GZ1 0 VY1 VZ1 0 1e-6
    C10 0 VY1 1e-12
    R33 VY1 0 1e9
    E9 N006 0 VY1 0 1
    
    G11 0 VZ2 VX2 VY2 1e-3
    RZ2 0 VZ2 1e9
    DSLEW3 VC2 0 DZ
    DSLEW4 VC2 VZ2 DZ
    GZ2 0 VY2 VZ2 0 1e-6
    C9 0 VY2 1e-12
    R31 VY2 0 1e9
    E10 N020 0 VY2 0 1
    
    *** OUTPUT STAGE WITH EXTRA POLES AND CAP RESPONSE ***
    VOS- N010 N006 27.158e-6
    VOS+ N024 N020 -27.158e-6
    V_Current_Sense- N008 N005 0
    V_Current_Sense+ N027 N022 0
    D1 N021 N019 DX
    D2 N028 N021 DX
    D3 P001 N007 DX
    D4 N007 P002 DX
    V1 P003 N019 .57837
    V2 N028 N029 .58737
    V4 N003 P002 .57837
    V5 P001 N014 .58737
    
    G8 0 N120 N007 N005 1
    R50 N120 0 1e9
    C50 N120 0 1.18e-9
    G9 0 N005 N120 0 8.33e-3
    R51 N005 0 120
    C51 N005 0 10e-12
    G12 0 N121 N021 N022 1
    R52 N121 0 1e9
    C52 N121 0 1.18e-9
    G13 0 N022 N121 0 8.33e-3
    R53 N022 0 120
    C53 N022 0 10e-12
    
    G6 0 N007 N012 0 1e-3
    G7 0 N021 N026 0 1e-3
    R29 N007 0 1e3
    R30 N021 0 1e3
    H1 N029 VN V_Current_Sense+ 13.1
    H2 VP P003 V_Current_Sense+ -17.42
    H3 N014 VN V_Current_Sense- 13.1
    H4 VP N003 V_Current_Sense- -17.42
    *R32 NC 0 1e6
    
    .MODEL DX D(IS=1e-15 RS=.1)
    .MODEL DN D(IS=1e-15 KF=2.1e-3)
    .MODEL DZ D(IS=1e-15 BV=24.5)
    
    .ends AD8475
    *$
    

    把txt文件修改成后缀名.cir,然后重新建立模型看看效果