Hello Guys,
I encounter one problem, which is the op-amp's output has a few DC offset. I don't know how to remove it, could any one help me on this?
Thanks inadvance!
Above is my simulation schematic, and the simulation result is below
Hello Guys,
I encounter one problem, which is the op-amp's output has a few DC offset. I don't know how to remove it, could any one help me on this?
Thanks inadvance!
Above is my simulation schematic, and the simulation result is below
Two Method：
1. Integrator can remove the offset(more details in the attachment),
2. add a programmable bias voltage through a resistor in the sum node (KCL theory) :
Two Method：
1. Integrator can remove the offset(more details in the attachment),
2. add a programmable bias voltage through a resistor in the sum node (KCL theory) :
