HMC863ALC4 的VDD对地电阻小的问题

请问VDD脚与地间电阻为2欧是该芯片的正常状况吗?

  • 0
    •  Analog Employees 
    on Sep 27, 2018 2:26 AM

    您好,请将您的问题发布在英文版块哦 ez.analog.com/.../

  • 0
    •  Analog Employees 
    on Sep 27, 2018 8:23 PM

    Hello zhan666,

    Your question appears in Chinese in my browser so, I used Google to translate your question to English as:

    "Is the VDD pin and ground resistance 2 ohms normal for the chip?"

    Here is my answer in English:

    Because this is a depletion mode device, if the gate is left open then the channel will conduct and thus the path from drain-to-ground will look like a low resistance. If Vgg were to be biased to an adequately negative voltage then the path from drain-to-ground will look like a high resistance.

    Using Google to translate my answer to Chinese (Traditional), I get:

    因為這是耗盡型器件,如果柵極保持開路,則溝道將導通,因此從漏極到地的路徑看起來像低電阻。 如果將Vgg偏置到足夠的負電壓,則從漏極到地的路徑看起來像高電阻。

    I hope that helps.

    Regards,

    SMcBride