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ADE9000 Fast RMS½ Measurement ,read register value of AIRMSONE always 0.?

ADE9000 考虑Fast RMS½ 采集数据,提高响应速度。但目前读到的AIRMSONE为0。      读取AIRMS是可以读取数据的。请帮看下是否需要设置哪些寄存器参数才可读取?

手册里面提到的寄存器有尝试设置,但无果:

Fast RMS½ Measurement
RMS½ is an rms measurement performed over one line cycle,
updated every half cycle. This measurement is provided for
voltage and current on all phases plus the neutral current. All
the half cycle rms measurements are performed over the same
time interval and update at the same time, as indicated by the
RMSONERDY bit in the STATUS0 register. The results are
stored in the AIRMSONE, BIRMSONE, CIRMSONE,
NIRMSONE, AVRMSONE, BVRMSONE, and CVRMSONE
registers. The xRMSONE register reading with full-scale inputs
is 52,702,092d.
It is recommended to select the data before the high-pass filter
for the fast rms measurement by setting the RMS_SRC_SEL bit
in the CONFIG0 register.
The LP_SEL bits in the ZX_LP_SEL register select which line
period measurement sets the number of samples used in the
rms½ measurement. Alternatively, set the UPERIOD_SEL bit in
the CONFIG2 register to set desired period in the USER_PERIOD
register for line period measurement. An offset correction
register is available for improved performance with small input
signal levels, xRMSONEOS.

  • 请把目前和RMS1/2配置相关寄存器配置值列一下

  • 寄存器配置:

    #define ADE9000_CONFIG0   0x00000080
    #define ADE9000_CONFIG1   0x0002
    #define ADE9000_CONFIG2   0x0C00
    #define ADE9000_CONFIG3   0x0000
    #define ADE9000_ACCMODE 0x0100
    #define ADE9000_TEMP_CFG    0x000C
    #define ADE9000_ZX_LP_SEL   0x001E
    #define ADE9000_MASK0   0x00000001
    #define ADE9000_MASK1   0x00000000
    #define ADE9000_EVENT_MASK   0x00000000
    #define ADE9000_VLEVEL     0x0022EA28
    #define ADE9000_DICOEFF   0x00000000

    #define ADE9000_EP_CFG      0x0011
    #define ADE9000_EGY_TIME  0x1F3F
    #define ADE9000_EP_CFG      0x0011
    #define ADE9000_EGY_TIME  0x1F3F
    #define ADE9000_WFB_CFG   0x1000

    初始化过程:

    ADE9000TempData.ul_Register= ADE9000_CONFIG0; 
    Write_ADE9000_SPI(ADDR_CONFIG0, 4, ADE9000TempData.uc_Register); 
    ADE9000TempData.ul_Register= ADE9000_ZX_LP_SEL; 
    Write_ADE9000_SPI(ADDR_ZX_LP_SEL, 2, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_CONFIG1; //
    Write_ADE9000_SPI(ADDR_CONFIG1, 2, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_CONFIG2; //
    Write_ADE9000_SPI(ADDR_CONFIG2, 2, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_CONFIG3; //
    Write_ADE9000_SPI(ADDR_CONFIG3, 2, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_ACCMODE; //
    Write_ADE9000_SPI(ADDR_ACCMODE, 2, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_TEMP_CFG; //
    Write_ADE9000_SPI(ADDR_TEMP_CFG, 2, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_MASK0; //
    Write_ADE9000_SPI(ADDR_MASK0, 4, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_MASK1; //
    Write_ADE9000_SPI(ADDR_MASK1, 4, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_EVENT_MASK; //
    Write_ADE9000_SPI(ADDR_EVENT_MASK, 4, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_WFB_CFG; //
    Write_ADE9000_SPI(ADDR_WFB_CFG, 2, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_VLEVEL; //
    Write_ADE9000_SPI(ADDR_VLEVEL, 4, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_DICOEFF; //
    Write_ADE9000_SPI(ADDR_DICOEFF, 4, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_EGY_TIME; //
    Write_ADE9000_SPI(ADDR_EGY_TIME, 2, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_EP_CFG; //
    Write_ADE9000_SPI(ADDR_EP_CFG, 2, ADE9000TempData.uc_Register);
    ADE9000TempData.ul_Register= ADE9000_RUN_ON; //
    Write_ADE9000_SPI(ADDR_RUN, 2, ADE9000TempData.uc_Register);

  • #define ADE9000_ZX_LP_SEL   0x001E  I think this is combined zx  

    #define ADE9000_ZX_LP_SEL   0x0000  Can you try just using phase A

    How are you monitoring RMSONERDY to determine when to read the 1/2 cycle rms? the IRQ is not enabled in the mask0 register. 

    Dave