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Clock and Timing
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Documents AD9510: datasheet appears to contradict evaluation board schematic which uses balun for single ended ref clock connection.
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  • +Documents
  • AD9508 in CMOS Single-Ended Output Configuration
  • AD9510 Register Configuration Reset
  • AD9510: datasheet appears to contradict evaluation board schematic which uses balun for single ended ref clock connection.
  • AD9510: Evaluation PCB
  • AD9510: Outputs not in Phase
  • AD9511: Programming the device in RESET
  • AD9512 evaluation board and  Windows 7, 64 Bit driver issues
  • AD9512 evaluation software and windows 7 64bit compatibleissues
  • AD9512 Phase setting not working
  • AD9513: figure 25 full scale delay datasheet error
  • AD9515_power consumption with divider ratio
  • AD9517-1 delay to output of channel divider
  • AD951x: REFIN & CLK levels and FAQ "how to treat unused pins"
  • AD9520-3 EEPROM settings aren't loaded
  • AD9523-1: Can I bypass PLL1 and only use the PLL2?
  • AD9548 v AD9518, comparison of phase noise performance
  • AD9548: JTAG simulation file
  • AD9549BCPZ:P CMOS does not have output
  • AD9552 loop bandwidth and PFD rate?
  • ADCLK846: broadband jitter description
  • Additive and Absolute Jitter
  • Baking the AD9951A
  • Clock and Timing Support Community
  • FAQ: Does the AD9523, AD9524, or AD9523-1 have glitchless switchover?
  • HMC7044, HMC7043 vs LTC6952, LTC6953
  • Holdover/Switchover Functionality
  • Jitter over Multiple Bandwidths
  • LTC695x Low Frequency Phase Noise Measurement Issues
  • LVDS specifications
  • RE: AD9514 synchronisation setup and hold times of SYNCB with respect to CLK/CLKB
  • Want to use AD9510/11's DLD as our lock alarm, but it may not work properly if the reference disappears. Any solution?
  • What's the best way to connect a 3.3V CMOS clock signal to SYSCLK?
  • Why is the minimum Input Frequency for the Single-Ended Mode REF1 and REF2 AC-Coupled only 20MHz?

AD9510: datasheet appears to contradict evaluation board schematic which uses balun for single ended ref clock connection.

Q 

There appears to  be a contradiction between the datasheet and the evaluation
board documentation / schematic with regards to the use of a balun for single
ended reference clock connection.

The AD9510 datasheet says: If REFIN is driven single-ended, decouple the unused
side (REFINB) via a suitable capacitor to a quiet ground.

However the AD9150 evaluation board uses a balun to connect to a single ended
reference clock.

Why is that? Is it sufficient to do it without a balun, as it is described in
the datasheet?

 

A 

We use baluns on the evaluation board for the reference inputs because we
typically drive the input with a single ended high end SMA 100 signal
generator. So, the balun allows for more differential swing at the DUT and
higher slew rate too. That’s why we baluns. That said, it’s fine to drive the
reference input single ended and tie off the unused reference input side as
described in the datasheet.
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