Q
I am using AD9510, AD9511, AD9512 and AD9951. I would like to ask the following:
1) About CLK1, CLK2, REFIN inputs in AD951x and REFCLK input in AD9951, do they
accept both sinusoidal and square signals, like LVPECL?
2) Which is the maximum input level at REFIN input in AD9510/AD9511?
3) In some components, I am not going to use some of the following pins:
*) CLK1/CLK1B, CLK2/CLK2B inputs at AD951x.
*) REFIN/REFINB input at AD9510/AD9511.
*) Some LVPECL outputs at AD951x.
*) Some LVDS/CMOS outputs at AD951x.
*) STATUS at AD951x.
*) VCP and CP at AD9510/AD9511 (if I don't use the PLL).
*) DSYNC/DSYNCB at AD9512.
*) SYNCK_IN at AD9951.
*) LOOP FILTER at AD9951 (I won't use the internal multiplier).
*) CRYSTAL_OUT at AD9951.
What should I do with those pins? Should I leave them unconnected?
A
1) Yes.
a) The DDS AD9951 DDS outputs must be tied high - to the power supply - through
a proper current path. This is necessary because the DDS is a current output
DAC.
b) The DDS output must be low-pass reconstruction filtered to restore a smooth
sinewave. This is necessary. Otherwise a great deal of jitter will be
introduced once you apply the signal to the clock distribution.
The DDS data sheet shows the type of filter needed.
c) The CLK1/CLK2 inputs on the AD951x are self-biased. So, it is probably best
to AC couple the signal from the DDS filter to the CLK1 or CLK2 input. This
assures that the sinewave will be seen symmetrically by the AD951x input.
2) The REFIN level should stay within the levels of ground and the Vs supply
voltage.
There are ABSOLUTE MAXIMUM levels shown on page 18 of the AD9510 datasheet (up
to 300 milliVolts beyond the supply) but these are stress levels only and not
for normal operation.
The preferred REFIN level is not a simple answer. In general, the best level is
the highest that doesn't exceed the excursion limits.
A better question is this:
What level for this signal do you have available?
If it is in the allowed input range, then use it.
If it is not within the allowed range, then you'll have to work out how to get
it within the range, and what the effect of that would be.
3) Whichever clock input which is not being used should be powered down to
avoid possible chatter and/or crosstalk.
This is easily done by setting a bit in the programming registers.
In some components, I am not going to use some of the following pins:
*) CLK1/CLK1B, CLK2/CLK2B inputs at AD951x.
>>>> If one of these inputs is not used, then power it down. It doesn't have to
be connected if it is not used.
*) REFIN/REFINB input at AD9510/AD9511.
>>>> If the PLL is not being used, it should be powered down (default). If the
PLL is powered down, then the REFIN input does not have to be connected.
*) Some LVPECL outputs at AD951x.
>>>> Any unused outputs of AD951x should be powered down, and do not have to be
connected.
*) Some LVDS/CMOS outputs at AD951x.
>>>> Any unused outputs of AD951x should be powered down, and do not have to be
connected.
*) STATUS at AD951x.
>>>> If the STATUS pin is not used, it can be left not connected.
*) VCP and CP at AD9510/AD9511 (if I don't use the PLL).
>>>> If the PLL is not used, the PLL should remain powered down (default). The
VCP and CP do not need to be connected.
*) DSYNC/DSYNCB at AD9512.
>>>> The DSYNC/DSYNCB do not need to be connected.
*) SYNCK_IN at AD9951.
>>>> If the SYNC function is not being used, the SYNC_IN does not need to be
connected. See CFR1<23>.
The SYNC_IN input, when the SYNC function is not used, is a powered down
digital gate.
Grounding it or leaving it disconnected are actually both fine.
*) LOOP FILTER at AD9951 (I won't use the internal multiplier).
>>>> If the internal multiplier is not used, the LOOP_FILTER pin does not have
to be connected. It has an internal pull-up to AVDD.
*) CRYSTAL_OUT at AD9951.
>>>> If not used, the CRYSTAL_OUT does not have to be connected.
If not using a crystal and the internal oscillator, this pin isn't connected to
anything. Leave disconnected.