In the datasheet, I don't find any register to disable the PLL1, so I am not
sure it is OK to bypass it.
Yes the AD9523, AD9523-1, and AD9524 can all be configured as a single loop
device and offer a low power clock generator distribution solution.
To use only the second loop PLL(2) the input reference to the PLL would be the
OSC_IN input(s) either configured as single-ended CMOS or differential. There
is a power down bit for PLL1 but this can NOT be used because it will also
power down the OSC_IN input receivers. To save power individual PLL1 blocks
can be powered down: REFA and REF input receivers (reg h01A), Charge pump
current set to 0 and tristate (reg h018 and h019), and Zero Delay receiver (reg
To use only the first loop PLL(1) Outputs 0, 1, 2, 3 on the AD9523 and AD9523-1
can be configured to output PLL1. The AD9524 Outputs 0 and 1 can be used to
output PLL1. To reduce power disable: power down unused output channels,
Charge pump current set to 0 and tristate (reg h0F0 and h0F2), VCO divider (reg
h0F4), and Zero Delay receiver (reg h01B).