AD9523-1 interfacing with HMC832, DAC/ADC- input and output considerations

Question 1. We will plan to feed HMC832 with 50 Mhz REF clock. And our design will include 3 pieces of HMC832. So we don't want to delays between REFClocks. And our design also includes a clock generator/distributor. And clock generator/distributor is able to give LVPECL/LVDS/HSDS output. So weare not able to feed with Sinusoidal wave. There is a option to change clock distributor which is able to give LVCMOS output. So we haveLVPECL/LVDS/HSDS/LVCMOS signal types to feed HMC832.Could you able to say which signal type is suitable for HMC832? LVCMOS parameters match with datasheet values. Are we right?(See the answer for the first part below to understand the second question) 2. We try to find a jitter cleaner clock distributor for our ADC, DAC and PLL+VCO. Firstly clock distributor have to provide clean up andaccept sine wave input and LVDS input. So can we apply 10 MHz LVDS and Sine wave to AD9523-1's reference input? And also we will use HMC832as PLL+VCO. Previously we asked HMC832 reference input type, LVCMOS was recommended. So Is AD9523-1 LVCMOS suitable for HMC832 reference input? Answer 1. You are correct. Use a LVCMOS driver with 100? termination resistor at each HMC832. The LVCMOS driver meets the minimum signal level requirementsbut may overdrive the reference input without the 100? termination resistor. We find this scheme works well with our eval boards but in general anydesign that meets the specified levels in Table 8 will work. LVPECL/LVDS/HSDS drivers do not provide the necessary output swing.Figures 34 and 37 in DS show better FOM numbers with 50MHz square wave references. This is due to the fast edge rates compared to a sine wave butthere is a concern. A well terminated and isolated reference transmission line will perform well but the fast edges at higher reference frequenciesmake terminating this line difficult. For example we need a 100? resistor to reduce the signal amplitude on the LVCMOS driver but this does notprovide a perfect match to a 50? transmission line. Extremely fast edge rates with this design will not perform well – especially if thetransmission line is long and/or not isolated from other signals . This is the reason we prefer sine waves for higher frequency references as statedin Table 8. 2. My understanding based on Q1 and Q2 looks like this-(10MHz LVDS or sine wave to) AD9523-1 è ADC/DAC and (50MHz to) 3x HMC832.·For 10MHz LVDS reference into AD9523-1, yes, it is fine.· For 10MHz sine wave, if sine wave has 0dBm power level into 50ohm load, then the slew rate is only 0.02V/nS, which is too low.· For 10MHz sine wave, if sine wave has 7dBm power level into 50ohm load, then the slew rate is only 0.55V/nS, which is ok. Extremely low slew rate on AD9523-1 reference input would cause in-band noise increasing. I attached a PDF file to show if input slew rate is low,the impact on output in-band noise. In this case, AD9523-1 first PLL may set to a narrow loop bandwidth (such as 100Hz or so), but its outputperformance is still impacted within the bandwidth. You need to pay attention to this degradation. Let's look at HMC832's input : Though it did not specify the common-mode voltage on the input, from the Table8, HMC832 DS on Reference Sensitivity- we can see maximum square-wave input swing is 2.5V, which implies at AC-coupling condition, +/-1.25V around the common-mode so that the ESD diodesare not turned on. We can use this information to design the drive signal (from AD9523-1). An easy way, as we discussed previously is to use LVCMOS output format on AD9523-1 to drive REF-IN on HMC832. The problem is the loading – generallyspeaking, all CMOS drivers are NOT designed to drive heavy loading such as 50 ohms, but to drive capacitive loading, such as 10pF. AD9523-1’s CMOSoutputs are same, and they are NOT designed for heavy loading. Since AD9523-1’s CMOS output swing is 3.3V which is greater than what HMC832 can handle, we can use a resistor divider to divide down the swing andto increase the load resistance (reduce the loading). For example, we can place the external 100 ohm in series with the signal path (instead of inparallel with the REF input pin to GND on HMC832). This would reduce the swing roughly to 50% of 3.3V, but increase the load resistance to 200 ohmtotal. For 50MHz signal frequency, the HMC832’s input capacitance 5pF should be included in the simulations to determine the total loading forAD9523-1’s CMOS driver. Typically, such REF input likes to see near to maximum large swing on it, so you can adjust the series resistance value toget slightly larger swing than 50% of 3.3V. In any cases we discussed (add 100 ohm series R or slightly reduced series R), the total load resistance(or total load including capacitance) of the CMOS driver should be > 100 ohm (roughly around 150 ohms), which is ok for AD9523-1 (better than 50 ohmsloading). Another small suggestion is Don’t design 50 ohm PCB trace for CMOS driver, instead, design something with less capacitance (which means something hashigh impedance – small trace width means less capacitance but high impedance). This is because CMOS driver is NOT designed for 50 ohm loading.

AD9523-1: Can I bypass PLL1 and only use the PLL2?

Question Can I can bypass the PLL1 in AD9523-1 and input a ref clock at the OSC pins directly? In the datasheet, I don't find any register to disable the PLL1, so I am not sure it is OK to bypass it. Answer Yes the AD9523, AD9523-1, and AD9524 can all be configured as a single loop device and offer a low power clock generator distribution solution. To use only the second loop PLL(2) the input reference to the PLL would be the OSC_IN input(s) either configured as single-ended CMOS or differential. There is a power down bit for PLL1 but this can NOT be used because it will also power down the OSC_IN input receivers. To save power individual PLL1 blocks can be powered down: REFA and REF input receivers (reg h01A), Charge pump current set to 0 and tristate (reg h018 and h019), and Zero Delay receiver (reg h01B). To use only the first loop PLL(1) Outputs 0, 1, 2, 3 on the AD9523 and AD9523-1 can be configured to output PLL1. The AD9524 Outputs 0 and 1 can be used to output PLL1. To reduce power disable: power down unused output channels, Charge pump current set to 0 and tristate (reg h0F0 and h0F2), VCO divider (reg h0F4), and Zero Delay receiver (reg h01B).

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