AD9510: Evaluation PCB

Question 1 . Is the output for the external low pass filter a current or a voltage? 2. How is the maximum and minum voltage that can be presented in reference and CK2? 3. RcPSet in my case is 5.1 Kohm how can i change it? Answer Question 1: This is a Voltage ouput with a 100ohm Load. Question 2: The balum is a 1:1 balumn , therefore the spec's in the datasheet hold for this input - which is 150mV input range, as the Device is selfbiased. Question 3: See datasheet page 50 = CP_lsb = 3.06/CPRset - This is all you need to insert your own CPRset.

AD9510: datasheet appears to contradict evaluation board schematic which uses balun for single ended ref clock connection.

Question There appears to be a contradiction between the datasheet and the evaluation board documentation / schematic with regards to the use of a balun for single ended reference clock connection. The AD9510 datasheet says: If REFIN is driven single-ended, decouple the unused side (REFINB) via a suitable capacitor to a quiet ground. However the AD9150 evaluation board uses a balun to connect to a single ended reference clock. Why is that? Is it sufficient to do it without a balun, as it is described in the datasheet? Answer We use baluns on the evaluation board for the reference inputs because we typically drive the input with a single ended high end SMA 100 signal generator. So, the balun allows for more differential swing at the DUT and higher slew rate too. That’s why we baluns. That said, it’s fine to drive the reference input single ended and tie off the unused reference input side as described in the datasheet.

AD9510: Outputs not in Phase

Question for evalution board AD9510, on the CLK1 input 1001.6 MHz, ratio 8 for output5 and output6 equal 125.2 MHz. For on/off, on/off ext. clock (1001.6 MHz) have shift phase between output5 and output6 equal 90 or 180 or 270 or 0 degree. Answer It is necessary to do a register update AFTER each write to the Soft Sync bit. That is, it is necessary to load the Soft Sync bit by updating the registers with the 0x5A=1. Here is my recommended sequence: 1) write all of the desired parameters for the AD9510 2) write 0x5A=1 (update internal registers) 3) write 0x58 4) write 0x5A=1 (update internal registers) 5) write 0x58 6) write 0x5A=1 (update internal registers) Try this and see if it fixes the problem.

AD9510 Register Configuration Reset

Question Is there some way to hard reset the PLL counters without losing all register configurations? Answer Register 0x09 has bits to hold the R and N dividers in reset. You can set and clear these to get different phases.

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The AD9510 provides a multi-output clock distribution function along with an on-chip phase-locked loop (PLL) core. The design emphasizes low jitter and...
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