IEEE 1588 PTP + SyncE synchronization

Hi,

we do not have drivers to implement IEEE1588. 

I already sent you a paper in your previous EZ question:  AD9545 Small Cell / IEEE1588 application more complex explanation 

I continue to believe you should use it to understand how to implement the IEEE 1588 servo with the AD9545.

If I can provide more color to that document thinking at your case:

- that paper and AD9545 rev C data sheet, page 163, figure 118 present an approach to implemented the IEEE 1588 servo. Use also figure 131, AD9546 rev 0 data sheet, page 195.

-provide at REFA an OCXO that you'll use with the auxiliary DPLL to stabilize the wonder effects of the 52 MHz crystal resonator.

- in your case, SyncE/CDR is 156.25 MHz. In the data sheets, it's 125 MHz.

- set the DPLL0 to create two 156.25 MHz in phase buildout. If you need phase alignment of the outputs relative to the reference clock, set DPLL0 in internal zero delay.

- the controller has to provide GigE PHY IEEE 1588 PHY-1PPS to the AD9545. Provide it at one of the Mx pins in CMOS format. 

-use the AD9545 auxiliary TDC to time stamp the 1PPS signal. Controller reads these time stamps and compare the derived 1s period against 1s period of a GPS. 

-set DPLL1 to function using an auxiliary NCO as reference clock. Controller adjusts the AD9545 auxiliary NCO frequency to obtain OUT1A or OUT1B=1Hz of the same period as the GPS clock. Another way would be to set DPLL1 in free run and adjust the free running tuning word. Care must be taken to make the steps small enough to not unlock APLL1

Note that implementing such a servo into the AD9545 is only a very small effort. The great effort is implementing the 1588 standard into the controller.

"The essential question is what more has to be implemented to get PTP synchronization?" 

This is what I believe you should implement, but because I only support the AD9545, I do not know IEEE 1588 standard to speak comprehensively.

"I know that for example in the Renesas ClockMatrix IEEE Synchronizers device family the whole solution is based on above approach (but without 1 PPS signal, only 156.25 MHz signal going in the loop between external; ) "

This seems like another architecture in which SyncE clock is available, but 1588/PTP servo is unavailable. In that case, no frequency tuning is done. The AD9545 DPLLs lock onto SyncE and output the local PTP clock. 

Petre

Dear Sir,


Thank you for the more comprehensive answer but I stil have a feeling of missing couple of details - maybe if'd try to answer for them too, I'll get already the full picture:

1. Suppose I have at one of the AD9545 Mx pins GigE PHY IEEE 1588 PHY-1PPS - why should I compare it to the 1 PPS signal from GNSS (GPS) on the other Mx pin? For me it's messing up two different synchronization scenarios: so called LLS-C1 (when 1 PPS signal is coming from the physical layer link so GigE PHY IEEE 1588 PHY-1PPS in this case)  and LLS-C4 (when 1 PPS signal is coming from the GNSS network so 1 PPS GPS in this case) in the ORAN synchronization scenarios. Can't I just use one of these 1 PPS (from IEEE 1588 PHY or GPS) as the phase reference?

2. I think you didn't mention it in the answer - you only wrote about obtaining 1 Hz (PPS) output on OUT1A/B. But what about different frequencies? To be specific I woud like to get output frequency of e.g. 7.68 MHz, 122.88 MHz which then would serve as reference for the next stage Jitter clenaer which provides reference and SYSREF signals. Would this signals be then phase aligned to this 1 PPS in the input? The whole idea of SYSREF (and JESD204B) is to have deterministic phase/frequency relationship so it's quite crucial.

3. In the sent document you mentioned that GigE PHY IEEE 1588 PHY-1PPS goes into one of the Mx pins and the it goes as (loopback?) reference to the CPU - why provide loopback 1 PPS to the CPU when the adjustment is made in the AD9545? To compare on CPU whatever the coming 1 PPS loopback singal is already phase aligned?

4. Could you provide more detail description of the "cascade" operation you mentioned in the sent additional document? Would it allow eventually both PLL1 and PLL2 outputs to be phase aligned to the 1 PPS signal?

5. Last but not least - there are offcial AD's Linux drivers for the AD9545 but how about AD9546 beacuse I could not find them?

Best regards 

HI,

I told you I am not a specialist of IEEE 1588. I'll respond only to specific questions pertaining to the AD9545 behavior.

" I think you didn't mention it in the answer - you only wrote about obtaining 1 Hz (PPS) output on OUT1A/B. But what about different frequencies? To be specific I woud like to get output frequency of e.g. 7.68 MHz, 122.88 MHz which then would serve as reference for the next stage Jitter clenaer which provides reference and SYSREF signals. Would this signals be then phase aligned to this 1 PPS in the input? The whole idea of SYSREF (and JESD204B) is to have deterministic phase/frequency relationship so it's quite crucial."

Just set the DPLL1 to lock in internal zero delay mode and you can create any frequency that is an integer multiplier of 1 Hz. The outputs will be phase aligned to 1 Hz.

" Could you provide more detail description of the "cascade" operation you mentioned in the sent additional document? Would it allow eventually both PLL1 and PLL2 outputs to be phase aligned to the 1 PPS signal?"

There is an entire section in the rev C AD9545 data sheet page 112. Look for the explanations of figure 85 at page 113. If you have both DPLLs locked onto the same reference clock, when the reference clock becomes invalid, both DPLLs would enter holdover and the outputs of each DPLL are not anymore phase locked. By creating a profile on the cascaded (i.e. second) DPLL that uses the feedback clock of the first DPLL, only the first DPLL enters holdover. The other locks onto the first DPLL feedback clock, so the outputs of both DPLL remain phase locked.

AD9545_in_cascaded_mode_20260820.pdf

The attached paper gives details about how to configure this into ACE.

"there are official AD's Linux drivers for the AD9545 but how about AD9546 because I could not find them?"

I do not know anything about these drivers. What I can tell you is that the AD9546 is backwards compatible with the AD9545, that is the AD9545 registers are also in the AD9546. So I suppose the AD9545 drivers could be used in the AD9546 as well.

Petre

Dear Sir,

Ok, I understand. May you eventually point any place in the forum/AD site (or maybe contact to any person from AD) who could help more in terms of using this AD9545/6 part in the IEEE 1588 application?

Best regards

Hi,

If you have specific questions about the behavior of the AD9545, I can certainly respond. But I'm afraid that for IEEE 1588 related questions, there are no resources that I can think to. I gave you all the documentation I give to customers interested in using the AD9545 or AD9546 into an IEEE 1588 servo.

Petre

Hello,

Sorry for coming back after a short time but I'd have one more question regarding the document you've sent me "More details about IEEE 1588 Servo implementation from the AD9545 data sheet " - you mention there that for the REFA/AA stable 10 MHz signal should be apllied whereas for the one of the Mx pins - 1 PPS signal. Can it be eventually done the opposite way, I mean 1 PPS applied to the REFA/AA and 10 MHz OCXO compensation signal to Mx pin, in this scenario?

Best regards

Hi,

sorry for the delay in getting back to you. I was out of office.

Sure, you can change where you apply the clocks. Just be aware that the clocks applied at Mx pins must be CMOS with the high level determined by VDDIOA and VDDIOB:

You have a far more variety of choices when you apply clocks to REFA/AA. See the spec table in rev C AD9545 data sheet pages 12 and 13.

Petre