Category: Hardware
Product Number: HMC7044
Dear Engineer:
We are using the HMC7044 to generate the clocking system for the JESD204B interface. The clock signal generated by the VCXO output of PLL1 is LVPECL level. How should the LVPECL signal be connected to the OSCIN input? Is a termination resistor required? Is there any reference design available? Also, how should the configuration options highlighted by the red box in the figure below be configured?
