AD9545 Small Cell / IEEE1588 application more complex explanation

Dear Sir,

I've been struggling with understanding the whole concept of AD9545 working in the small cell application which is shown in the Fig. 117 in the datasheet and I was hoping you could give me more complex explanation of it. For the sake of simplicity let's assume that the input reference (entering for example REFA/REFAA input) signal is 156.25 MHz SyncE signal from the external network. Following the example frequencies (greyed out ones) given in the mentioned picture let's further assume that from the OUT1A/OUT1B outputs exit 156.25 MHz signals to the "Network Connection" block and further again to the "External Network" block (so basically in the loop). The other OUTPUTS (OUT0A, OUT0B, OUT0C) outputs have frequencies: 7.68 MHz, 122.88 MHz, 245.76 MHz. Could you please provide with the more complex answers for the following questions regarding this configuration?

1) What is the purpose of creating the loop of 156.25 MHz frequency when External Network acts as a main controller and is the node that sources the frequency to the AD9545 - why is this backloop coming out of the AD9545 to the External Network?
2) Because I believe it is not directly pointed out in this picture - since input/output (from PLL1) are the same frequency so are they are in ZDM mode? And also since there is a fractional relationship between output frequencies of PLL0 and reference (REFA) the phase aligment between them is not preserved. In such apllication as shown here this lack of phase synchronization for those signals is not a problem?

I'm also not sure of the application shown in the Fig. 118. (Using an AD9545 in an IEEE1588 Version 2 Application) and I have also some questions regarding this configuration:

1) Why there are two reference input simultaneously? What should be the frequency range of the signal entering the REFB/REFBB pins? Is this signal also supposed to be of SyncE standard?
2) Are these two 1 PPS signals going to the Mx pins used for closed loop compensation mechanism?
3) Why there is also loopback signal going out of the AD9545 (PLL0) and enetring this external timing device?
4) What are the phase dependencies between input signals and output signals in this application (REFA/AA and REFB/BB vs outputs of the PLL0 or PLL1)? Are any of them configured in ZDM?








Best regards