ADCLK946BCPZ – No Differential Output with AC-Coupled Single-Ended Input

HI,

why did you put VEE pins to ground through C109 capacitor? Why did not connect them directly to ground? Look in UG-069 (make a search on analog.com website for it) and see on the eval board, it is recommended to connect VEE to ground:

Then, I did not see the 100 ohm resistor placed between the outer terminals of C42 and C43. If you put the scope probe on TP35 and TP36, set the scope on 50 ohm input impedance.

Petre

Hi Petre,

Thank you for your quick response.

I followed the ADCLK946 EVK schematic, where VEE is connected to GND through a 10 µF capacitor. However, I removed the capacitor and connected VEE directly to GND, and now I am able to observe the 10 MHz output signal.

Also, please note that the 100 Ω differential termination is placed at the receiver side. I did not include it in the schematic that I previously shared.

I have one more question regarding the input configuration. I would like to apply a 1 Hz single-ended CMOS input signal to the ADCLK946 while keeping the output as LVPECL.

Could you please confirm whether Figure 22 (Interfacing to AC-Coupled Single-Ended Inputs) in the ADCLK946 datasheet is still applicable for a 1 Hz CMOS input signal? Since the input frequency is very low, I am unsure whether the AC-coupled input configuration is appropriate or if a different input interface is recommended.

Additionally, could you please advise on the recommended input configuration for a 1 Hz single-ended CMOS input? Also, could you confirm whether the existing LVPECL output configuration is appropriate for this application?

Thanks in advance for your support.

Regards,

Abishek

Hello Petre,

Could you please clarify the request.

Regards,

Abishek

Hello Analog team,

Anyone could help on this?

Regards,

Abishek

HI,

sorry for the delay in getting back to you.

The data sheet says the ADCLK946 accepts DC coupled, single ended, 3.3V CMOS clocks. But it does not give a recommended schematic. 

The ADCLK948 data sheet gives this schematic for the 3.3V CMOS DC coupled, single ended input:

I believe you should apply this approach.

"Also, could you confirm whether the existing LVPECL output configuration is appropriate for this application?"

This buffer outputs LVPECL signals, which I am not sure if they make sense for 1Hz clocks, which usually are CMOS clocks.

If you are looking for a 3.3V buffer that can receive 3.3V 1Hz clock and outputs 3.3V CMOS clocks, than look at the AD9513. Has two CMOS outputs, one of which is opposite of the other (i.e. complementary). The input, even if 3.3V CMOS, must be AC coupled.

The AD9508 can output 1.8V CMOS clocks. It can receive 3.3V CMOS clocks and output 1.8V CMOS clocks when the outputs are set as HSTL and do not have 100 ohm loads.

Petre

Hi Petre,

Thanks for your response.

On the receiver side, the IC supports LVPECL, and the hardware has already been manufactured. Therefore, I am unable to change the LVPECL interface to a different logic level.

I also tried the DC-coupled input configuration as shown in Figure 23 of the ADCLK948 datasheet, along with the DC-coupled output configuration shown in Figure 15 of the ADCLK946.

However, I still observe only a short pulse of approximately 25 µs at the output instead of the expected 1 Hz waveform. Please refer to the attached image.

To further understand the device behaviour, I gradually increased the input frequency. I observed that from approximately 50 kHz onwards, the ADCLK946 reproduces the input waveform correctly.

Could you please share your thoughts on this behaviour? Is there any limitation of the ADCLK946 at very low input frequencies, or is there an alternative configuration that you would recommend?

Thanks!

Regards,

Abishek

HI,

what is your configuration of the outputs? They should be DC coupled for 1 Hz clock. A 50 kHz clock has a period of 20us, shorter than the 25 us you see for 1 Hz. I therefore suppose you use AC coupling, which then creates only some shorter pulses for 1 Hz.

Petre

Hi Petre,

Output side I followed Figure 15: DC -coupled 3.3V LVPECL far-end Thevenin Termination.

Regards,

Abishek

HI,

I have to replicate your issue on an eval board and then get back to you

Petre

HI,

it seems your company is using another channel to communicate with our support engineers. It does not make sense to use two separate channels to require support for the same issue. The support will be provided through the other channel.

Petre