PLL Locking and the SYSREF

Hi,

you may leave the SYSREF_IN pins 70 and 71 floating, but power down the SYSREF_IN receiver by setting bit 2 in register 0x0404 to 1 when you initialize the AD9528

Petre

Hi 

Thanks for the reply 

we have  connected pin 70 & 71 to ground through 0.1 µF capacitors to avoid noise.

Since you recommended leaving these pins floating, should we completely remove these capacitors from the design? Will keeping the capacitors cause any issues with the chip.

Hi,

the capacitors do not matter. If you populate them, no problems will be created to the AD9528. Just set bit 2 in register 0x0404 to 1 when you initialize the AD9528.

Petre

Hi,

Thanks for the reply

I am using ADIsimCLK to design an external loop filter for a 32 MHz TCXO and 122.88 MHz VCXO setup. However, the simulation giving  a error at the VCO frequency stage. How can I resolve this configuration issue?"

My recommendation is to use the AD9528 evaluation software (that you may download from here: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9528.html#eb-relatedsoftware) to find the desired AD9528 configuration. Even if you do not use an eval board, you can still use it stand alone.

I see you want to use a reference clock of 32 MHz, but it is not clear to me what output frequencies you want.

In ADIsimPLL you set the VCXO as 122.88MHz, so I suppose you use such a VCXO on your board.

PLL1 is configured correctly. 

This is how you should think in how to configure PLL2:

- Let's say the output frequencies have the least common multiple OUT. 

- The PLL2 VCO may have any frequency between 3.45 GHz and 4.025 GHz. You then obtain an array of integers between 3.45GHz/OUT and 4.025GHz/OUT. If there is no integer that can be extracted, there is no solution.

You then have this equation you need to satisfy: VCXO/R1*Doubler = VCO/M1/N2

R1 is a number between 1 and 31.

Doubler may be 1 or 2 (if you disable it or not).

M1 may be 3,4, or 5.

N1 comes out as a result. It must be between 16 and 255. Otherwise there is no solution.

VCO is the value of one of the integers above multiplied by OUT.

If you tell me the output frequencies, I can make these calculations for you.

Petre 

Hi,
Thanks for the reply.
I need to generate the 245MHZ output clock 
and also can you please suggest the calculation application note for the external loop filter.

HI,

I'm sorry to say, but with a 122.88MHz VCXO, you cannot generate 245 MHz.

If you use a 100 MHz VCXO, then you can:

PLL1 Components: RA=8, N1=25

You would have several choices for PLL2:

1) PLL2 Components: VCO=3675000000.0, R1=4, Doubler=1, N2=49, M1=3, OUT0 divider is:5 

2) PLL2 Components: VCO=3675000000.0, R1=20, Doubler=1, N2=147, M1=5, OUT0 divider is:3

3) PLL2 Components: VCO=3920000000.0, R1=10, Doubler=2, N2=49, M1=4, OUT0 divider is:4 

There is no external loop filter for the AD9528. If you enter on analog.com site and make a search for "phase locked loop" and in Resources section on the left side, you clock Technical Documentation, you'll find several PLL tutorials that speak about loop filters as well.

Petre