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AD9528 Recommended for New Designs
The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
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AD7768 Recommended for New Designs
The AD7768/AD7768-4 are 8-channel and 4-channel 24-bit, simultaneous sampling, sigma-delta (Σ-Δ) analog-to-digital converters (ADCs) with power scaling...
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AD9528 SYSREF / SYNC polarity inversion for AD7768 active-low sync trigger

		
	
				

			

									
					    mmercan
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Jul 8, 2026 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user is using the AD9528BCPZ for clock distribution and synchronization of AD7768 ADCs, requiring a 32 MHz MCLK and two successive active-low sync pulses. The AD9528 does not support output polarity inversion, but the AD7768 synchronization is triggered by the rising edge of the sync pulse, making the polarity less critical. The user should verify with AD7768 support if two active-high pulses from the AD9528 can meet the system requirements.
                        	    

                
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Category: Software

    		        		            		    
Product Number:  AD9528  

    		        		    		    

		    		    
		    			

			    
Hello Analog Devices team,


I am using an AD9528BCPZ as a clock distribution device in a system with AD7768 ADCs. The MCU is an STM32F446ZET6, and the firmware is generated in STM32CubeIDE. I have two AD9528BCPZ for one of is MCLK distribution and the other one is for SYNC distribution. 


My clock distribution requirement is:




AD9528:
- Generate/distribute 32 MHz MCLK to all ADC channels
- Generate two successive SYSREF/SYNC pulses for AD7768 synchronization
- The SYSREF/SYNC pulses must remain phase-deterministic with respect to the distributed 32 MHz MCLK




The system is very phase-sensitive; we are working at picosecond-level timing, so I cannot generate the sync pulses from an unrelated MCU GPIO or another asynchronous source. The sync pulse must remain inside the AD9528 clock/SYSREF timing domain.


The problem is the polarity of the sync signal required by the AD7768 side.


At the moment, the AD9528 internal SYSREF N-shot generator gives this waveform:




Current AD9528 SYSREF output:


LOW idle ________________|¯¯¯¯¯¯¯¯|________|¯¯¯¯¯¯¯¯|________________




However, the AD7768 synchronization input in my system needs an active-low sync pulse, so I need the opposite polarity:




Required waveform:


HIGH idle ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|________|¯¯¯¯¯¯¯¯|________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯




Important constraints:
























































1. I cannot solve this by swapping LVDS P/N lines in hardware.
2. I cannot generate the pulse directly from the STM32 GPIO, because that makes the sync timing independent from the AD9528 MCLK/SYSREF domain.
3. I need two successive pulses.
4. The sync pulse must remain deterministic relative to the AD9528 32 MHz clock outputs.




I also tried changing the AD9528 output channel source selection. For example, I tested the source option that appears to use SYSREF retimed by inverted PLL1 output. But it works like LOW idle mode. 



My master and sync profile:




const ad9528_reg_t ad9528_1_master_profile[] = {

    { AD9528_PLL1_REF_A_DIVIDER,   1u },
    { AD9528_PLL1_REF_B_DIVIDER,   1u },
    { AD9528_PLL1_FEEDBACK_DIVIDER, 5u },

    { AD9528_PLL1_CHARGE_PUMP_CTRL,
        AD9528_PLL1_CHARGE_PUMP_AUTO_TRISTATE_DIS |
        AD9528_PLL1_CHARGE_PUMP_MODE_NORMAL        |
        AD9528_PLL1_CHARGE_PUMP_CURRENT_nA(5000u)  },


    { AD9528_PLL1_CTRL,
        AD9528_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN |
        AD9528_PLL1_REF_MODE(REF_MODE_SELECT_REFA) |
        AD9528_PLL1_REFA_DIFF_RCV_EN              |
        AD9528_PLL1_REFA_RCV_EN                   |
        AD9528_PLL1_OSC_IN_DIFF_EN                 },

    { AD9528_PLL2_CHARGE_PUMP,
        AD9528_PLL2_CHARGE_PUMP_CURRENT_nA(805000u) },

    { AD9528_PLL2_FEEDBACK_DIVIDER_AB,
        AD9528_PLL2_FB_NDIV_A_CNT(0u) |
        AD9528_PLL2_FB_NDIV_B_CNT(10u) },

    { AD9528_PLL2_CTRL,
        AD9528_PLL2_CHARGE_PUMP_MODE_NORMAL },

    { AD9528_PLL2_VCO_CTRL, 0u },

    { AD9528_PLL2_VCO_DIVIDER,
        AD9528_PLL2_VCO_DIV_M1(5u) },

    { AD9528_PLL2_LOOP_FILTER_CTRL, 0u },

    { AD9528_PLL2_R1_DIVIDER,
        AD9528_PLL2_R1_DIV(1u) },

    { AD9528_PLL2_N2_DIVIDER,
        AD9528_PLL2_N2_DIV(8u) },

    { AD9528_CHANNEL_OUTPUT(0),  MCLK_32_CH },
    { AD9528_CHANNEL_OUTPUT(1),  MCLK_32_CH },
    { AD9528_CHANNEL_OUTPUT(2),  MCLK_32_CH },
    { AD9528_CHANNEL_OUTPUT(3),  MCLK_32_CH },
    { AD9528_CHANNEL_OUTPUT(4),  MCLK_32_CH },
    { AD9528_CHANNEL_OUTPUT(5),  MCLK_32_CH },
    { AD9528_CHANNEL_OUTPUT(6),  MCLK_32_CH },
    { AD9528_CHANNEL_OUTPUT(7),  MCLK_32_CH },

    { AD9528_CHANNEL_OUTPUT(8),  OFF_CH },
    { AD9528_CHANNEL_OUTPUT(9),  OFF_CH },
    { AD9528_CHANNEL_OUTPUT(10), OFF_CH },
    { AD9528_CHANNEL_OUTPUT(11), OFF_CH },
    { AD9528_CHANNEL_OUTPUT(12), OFF_CH },

    { AD9528_CHANNEL_OUTPUT(13), REF16_CH },

    { AD9528_CHANNEL_SYNC_IGNORE, 0u },

    { AD9528_SYSREF_K_DIVIDER,
        AD9528_SYSREF_K_DIV(512u) },
    { AD9528_SYSREF_CTRL,
        AD9528_SYSREF_SOURCE(SYSREF_SRC_INTERNAL)           |
        AD9528_SYSREF_PATTERN_MODE(SYSREF_PATTERN_NSHOT)    |
        AD9528_SYSREF_NSHOT_MODE(SYSREF_NSHOT_2_PULSES)     },

    { AD9528_CHANNEL_PD_EN,
        AD9528_CHANNEL_PD_MASK(0x1F00u) },

    { AD9528_STAT_MON0,   AD9528_STAT_PLL1_LD },
    { AD9528_STAT_MON1,   AD9528_STAT_PLL2_LD },
    { AD9528_STAT_PIN_EN, AD9528_STAT0_PIN_EN | AD9528_STAT1_PIN_EN },
};

const ad9528_reg_t ad9528_2_sync_profile[] = {

    { AD9528_PLL1_REF_A_DIVIDER,   1u },
    { AD9528_PLL1_REF_B_DIVIDER,   1u },
    { AD9528_PLL1_FEEDBACK_DIVIDER, 1u },

    { AD9528_PLL1_CHARGE_PUMP_CTRL,
        AD9528_PLL1_CHARGE_PUMP_TRISTATE },

    { AD9528_PLL1_CTRL,
        AD9528_PLL1_SOURCE_VCXO         |
        AD9528_PLL1_FEEDBACK_BYPASS_EN  |
        AD9528_PLL1_REFB_BYPASS_EN      |
        AD9528_PLL1_REFA_BYPASS_EN      |
        AD9528_PLL1_OSC_IN_DIFF_EN       },

    { AD9528_PLL2_CHARGE_PUMP,
        AD9528_PLL2_CHARGE_PUMP_CURRENT_nA(805000u) },

    { AD9528_PLL2_FEEDBACK_DIVIDER_AB,
        AD9528_PLL2_FB_NDIV_A_CNT(2u) |
        AD9528_PLL2_FB_NDIV_B_CNT(62u) },

    { AD9528_PLL2_CTRL,
        AD9528_PLL2_CHARGE_PUMP_MODE_NORMAL },

    { AD9528_PLL2_VCO_CTRL, 0u },

    { AD9528_PLL2_VCO_DIVIDER,
        AD9528_PLL2_VCO_DIV_M1(5u) },

    { AD9528_PLL2_LOOP_FILTER_CTRL, 0u },

    { AD9528_PLL2_R1_DIVIDER,
        AD9528_PLL2_R1_DIV(1u) },

    { AD9528_PLL2_N2_DIVIDER,
        AD9528_PLL2_N2_DIV(50u) },

    { AD9528_CHANNEL_OUTPUT(0),  OFF_CH },
    { AD9528_CHANNEL_OUTPUT(1),  OFF_CH },
    { AD9528_CHANNEL_OUTPUT(2),  OFF_CH },
    { AD9528_CHANNEL_OUTPUT(3),  OFF_CH },

    { AD9528_CHANNEL_OUTPUT(4),  SYSREF_CH },
    { AD9528_CHANNEL_OUTPUT(5),  SYSREF_CH },
    { AD9528_CHANNEL_OUTPUT(6),  SYSREF_CH },
    { AD9528_CHANNEL_OUTPUT(7),  SYSREF_CH },
    { AD9528_CHANNEL_OUTPUT(8),  SYSREF_CH },
    { AD9528_CHANNEL_OUTPUT(9),  SYSREF_CH },
    { AD9528_CHANNEL_OUTPUT(10), SYSREF_CH },
    { AD9528_CHANNEL_OUTPUT(11), SYSREF_CH },

    { AD9528_CHANNEL_OUTPUT(12), OFF_CH },
    { AD9528_CHANNEL_OUTPUT(13), OFF_CH },

    { AD9528_CHANNEL_SYNC_IGNORE, 0u },

    { AD9528_SYSREF_K_DIVIDER, AD9528_SYSREF_K_DIV(AD9528_SYNC_PULSE_WIDTH) },

    { AD9528_SYSREF_CTRL,
        AD9528_SYSREF_SOURCE(SYSREF_SRC_INTERNAL)                  |
        AD9528_SYSREF_PATTERN_MODE(SYSREF_PATTERN_NSHOT)           |
        AD9528_SYSREF_NSHOT_MODE(SYSREF_NSHOT_2_PULSES)             |
        AD9528_SYSREF_REQUEST_BY_PIN                                |
        AD9528_SYSREF_PATTERN_TRIGGER_CTRL(SYSREF_EDGE_RISING)      },

    { AD9528_PD_EN,
        AD9528_PD_PLL1 | 0x10u },  /* 0x10 = bias normal, bit2 = PLL1 PD */

    { AD9528_CHANNEL_PD_EN,
        AD9528_CHANNEL_PD_MASK(0x300Fu) },

    { AD9528_STAT_MON0,   AD9528_STAT_PLL2_LD  },
    { AD9528_STAT_MON1,   AD9528_STAT_VCXO     },
    { AD9528_STAT_PIN_EN, AD9528_STAT0_PIN_EN | AD9528_STAT1_PIN_EN },
};




Any clarification would be very helpful, especially whether this is fundamentally impossible in AD9528 or if there is a correct register-level configuration that I am missing.


Best regards.

			

			
									
		                             
                        

    

                                            
                 Analog to Digital Converters (ADCs)
                
                                                    
                 software
                
                                                    
                 Clock ICs
                
                                                    
                 ad9528
                
                                                    
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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Jul 8, 2026 9:02 AM
            
            
						
			            		
    
		
										+1
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi,
    

    please send me the stp file you created with the AD9528 evaluation software to obtain the AD9528 register configuration.
    

    Regarding " The SYSREF/SYNC pulses must remain phase-deterministic with respect to the distributed 32 MHz MCLK"
    

     
    

    There is the "Retimed by PLL2 output" option to select on the AD9528 output that you assign to be a SYSREF signal. In the eval software, it appears as SYSREF(Retimed by Divider Output).
    

    If you select this option, then the AD9528 generates the SYSREF pulses synchronous to the DEVCLK. When the data sheet says Retimed by divider output, it refers to the divider setup on the DEVCLK channel.
    

    Then, if you want to move the SYSREF clock relative to DEVCLK, you may use the Fine analog delay and Coarse analog delay.
    

    In the SYSREF channel, set the output divider equal to the divider you use in the DEVCLK channel for this to work.
    

    "the AD7768 synchronization input in my system needs an active-low sync pulse, so I need the opposite polarity:"
    

    I'm sorry, but the AD9528 does not have the option to invert the outputs. The "PLL1 output" in the driver options means the VCO. So when they say "inverted PLL1 output" basically they align the output to the negative edge of the VCO.
    

    If you configure the AD9528 to have the DEVCLK channel output divider equal to the PLL2 feedback divider and the VCO divider equal to 1, this means the DEVCLK output clock is in phase and og equal frequency to the PLL2 feedback clock after the N divider, that is at the PLL2 PFD input. Because PLL2 is locked, this makes the N divider output clock be equal to the VCO, which further means the DEVCLK output is equal to the VCO. If you select then the have the SYSREF retimed to the inverted PLL1 output, the SYSREF will be aligned to the negative edge of the DEVCLK, without employing the coarse and fine delays. 
    

    I looked at the AD7768 data sheet and it seems you refer to SYNC_INB signal. I suppose you employ the synchronization scheme from figure 111, page 75, rev D data sheet. At page 73, it seems to me the rising edge of SYNC_INB is what matters in the AD7768 behavior.
    

    So to me it does not matter that the AD9528 generates two active high pulses versus low active pulses. Important is for them to have two positive edges that come after two negative edges. It does not seem to be a specification for the timing between the negative edge and the positive edge: at page 18, t15 is 0 ns min, but it does not have a max. So maybe a repeated SYSREF train of one pulse followed by two pulses can create the situation you need.
    

    As I showed above, it is easy to align whatever SYSREF edge you need  to DEVCLK. Just ask the AD7768 support people what happens when the AD9528 generates two (or three) active high pulses to the AD7768 because they contain the positive edges it seems to me the AD7768 requires.
    

    Petre  
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Jul 8, 2026 9:47 AM
            
            
												
						in reply to pminc48
					
										
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi,
    

    Thank you for the detailed explanation.
    

    I understand your point now: the AD9528 cannot invert the output polarity internally, and the “inverted PLL1 output” option does not mean inverted SYSREF polarity. It only means that the SYSREF is aligned to the opposite edge of the retiming clock/VCO path.
    

    Regarding the .stp file: at the moment, my configuration is not generated directly from the AD9528 evaluation software. I am programming the AD9528 from an STM32F446ZET6 firmware using a register configuration based on the Analog Devices no-OS AD9528 driver.
    

    The current system architecture is:
    

    AD9528_1:
    - Uses VCXO / PLL configuration
    - Provides reference / clock to AD9528_2
    

    AD9528_2:
    - Generates 32 MHz DEVCLK/MCLK outputs for AD7768 devices
    - Generates two SYSREF/SYNC pulses using internal N-shot SYSREF
    - SYSREF outputs are routed to the AD7768 SYNC_INB pins
    

    My PC GUI only sends a SYNC command over RS485; the actual SYSREF generation is done inside the STM32 firmware and AD9528 register configuration, not by the GUI timing itself.
    

    Based on your explanation, I will configure the SYSREF output channel as: SYSREF(Retimed by Divider Output), and I will make the SYSREF channel output divider equal to the DEVCLK channel output divider, as you suggested.
    

    For my case, the target DEVCLK/MCLK frequency is 32 MHz.
    

    So my understanding is as follows:
    

    DEVCLK channel:
    - Source: PLL2 / divider output
    - Output divider selected for 32 MHz
    

    SYSREF channel:
    - Source: internal SYSREF
    - Output source: SYSREF retimed by divider output
    - SYSREF output divider = same divider value as DEVCLK channel
    - Use fine analog delay and, if applicable, coarse delay to align the required SYSREF edge relative to DEVCLK
    

    Please confirm whether this interpretation is correct for aligning the SYSREF edge to the 32 MHz DEVCLK edge.
    

    Regarding the AD7768 side: yes, I am referring to the SYNC_INB signal and the synchronization scheme similar to Figure 111 in the AD7768 Rev. D data sheet.
    

    Originally, I assumed the AD7768 required an active-low pulse in the sense that the low level itself was the important condition. However, after your explanation and re-reading the timing diagrams, I agree that the important event may actually be the rising edge of SYNC_INB, provided that it is preceded by a valid low level.
    

    One additional question for the AD9528 side:
    

    When using SYSREF(Retimed by Divider Output), and when the SYSREF channel divider is equal to the DEVCLK channel divider, are both the fine analog delay and coarse delay valid for moving the SYSREF edge relative to DEVCLK? Or is there any limitation when the channel source is SYSREF rather than a normal clock output?
    

    Thank you again for the clarification.
    

    Best regards.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Jul 8, 2026 3:23 PM
            
            
												
						in reply to mmercan
					
										
			            		
    
		
										+1
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    HI,
    

    "Please confirm whether this interpretation is correct for aligning the SYSREF edge to the 32 MHz DEVCLK edge."
    

    I confirm.
    

    "When using SYSREF(Retimed by Divider Output), and when the SYSREF channel divider is equal to the DEVCLK channel divider, are both the fine analog delay and coarse delay valid for moving the SYSREF edge relative to DEVCLK? "
    

    Yes, both fine analog delay and coarse delay work to adjust the SYSREF output relative to DEVCLK (if the divider in the SYSREF channel is equal to the divider in the DEVCLK channel). There are no limitations
    

    Petre
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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