The output cannot be synchronized with the input phase

Hi,

in the future, please send me the cso file you used to obtain the list of the AD9544 registers. 

Based on the ACE photo you sent, you seem to provide REFBB=100kHz and obtain at DPLL0 output OUT0A=1MHz and OUT0C=10MHz. You can set the DPLL0 to work in internal zero delay mode and this will make the OUT0A and OUT0C to be in phase to the REFBB=100kHz.

Petre

Thank you for your reply!
I have successfully achieved that when REFBB inputs 100KHz, OUT0A and OUT0C output waveforms in phase with it.
The next step is to achieve the same phase waveform of 80MHz and 100MHz output from OUT0A and OUT0C when REFBB inputs 1Hz. But I didn't succeed, please advise me again.
The ACE I am using is AD9545; On the PCB is AD9544
REFB input 100MHz 100ppb TCXO
The system crystal oscillator is 50MHz 100PPm
0x3008 is 0x10, 0x3007 is 0x10, and 0x3100 is 0x2C
Frequency locked, no phase locked
Also, I couldn't find a place to set 0x0800-0x0804 in ACE. May I ask where to set the Phase lock threshold.

Thanks again for the assistance.

.AD9545-1Hz.zip

HI,

I looked at the cso file you sent and it seems to me the AD9545 is correctly configured. You just need to provide REFBB=1Hz in 1.8V CMOS DC coupled (and make the schematic accordingly) from a GPS module or a rubidium or cesium based generator. What is your 1PPS source? Even if it is considered valid by the REFBB reference monitor, if REFBB wonders within the 100 ppm tolerance, the DPLL will not be able to lock.

 8585.AD9545 Live and Buffered Registers_20220118.pdf

I attach the list of live and buffered registers of the AD9545. The status registers you mention 0x3008, and 0x3007 are buffered. The 0x3100 register is live. A live register may be read at any time and it tells you the status in that moment. The buffered registers require executing first an IO Update operation (write 0x01 into register 0x0F) to latch the value of the status bits into the register. Then you read the register or registers. Did you execute an IO Update before reading 0x3007 and 0x3008?

The registers 0x800 to 0x809 are:

You click the blueish triangle near the REFBB (because this is the reference used in the DPLL0 Profile 0) and you get this:

You then change the desired parameters and then click Apply Changes. In my view, you only may want to change phase lock threshold, which at 700 ps may be too low. But I would not change the frequency lock threshold (you already got it locked) and the fill and drain rates. The fill and drain rates function at the carrier frequency used in the feedback clock, i.e. 10MHz in your case, which makes the lock to happen instantaneously when the bath tub (see DPLL lock detectors section the AD9545 rev C data sheet, page 99) starts to fill above the unlock level.

Petre

HI,

sorry for getting back to you so late.

I'm sorry to say, but the AD9544 was architected to maintain the output frequency no matter what. So if you want to be able to change the reference clock from 1 Hz to 2Hz and you also want the output o change from 80 MHz to 160 MHz, just create two configurations. You use the TDCs to measure the period of the reference clock and when the reference changes, just reinitialize the AD9545 with the related configuration. The output clocks will stop while this happens, but I do not believe it is a problem if you want to change the output frequency.

Petre