Hello everyone,
I am working on a design based on Analog Devices’ HDL project for the Zedboard, connected to an AD9434-FMC-500EBZ board (which includes an AD9434 ADC and an AD9517-4 clock synthesiser). I am having difficulty communicating via SPI under Petalinux (2025.2) with both components.
My current configuration:
- Hardware: The SPI controller on the PS (Zynq) is routed via the standard 4-wire EMIO interface (MISO, MOSI, SCLK and SS)
- As both ADxxxx components are configured in 3-wire SPI mode (SDIO), the HDL project uses a Verilog top-level file to convert the 4-wire signal from the Zynq into a 3-wire signal for the AD9434. This module uses a clock edge counter to toggle an IOBUF after the 16th bit, in order to multiplex the Zynq’s MOSI and MISO signals onto the single SDIO pin.
I have verified the SPI operation of the AD9434 using VITIS. However, I am encountering issues when switching to Linux
After generating the bitstream, I started by verifying the AD9434’s SPI operation with VITIS, and it works. However, my aim is to move towards a Petalinux configuration, and I am encountering issues.
I have added ADI/IIO drivers to the kernel:
- the AD9467 driver (for the AD9434), as supplied with Petalinux, simply enabled,
- the AD9517 driver was taken from Analog Devices’ Git repository, an external module was created and inserted into the build chain,
- axi-dmac and axi-adc-core for the PL side.
Then I turned my attention to the device tree. I looked through the driver code for the compatibility strings and created the two corresponding SPI devices. For the AD9517, I added `adi,spi-3-wire` to pre-configure the AD9517 HCIP in 3-wire mode. The AD9434 appears to be 3-wire only.
So once the project boots, I successfully test for the presence of the kernel modules (components and drivers).
However, I notice errors appearing in the boot sequence:
my_zed_project:~$ dmesg | grep -E "spi|ad9517|ad9467"
ad9517: loading out-of-tree module taints kernel.
ad9517 spi1.0: Unrecognized CHIP_ID 0xFF
ad9467 spi1.1: Mismatch CHIP_ID, got 0x0, expected 0x6A
I think the problem stems from the 3-wire SPI management.
Is it possible that the Linux driver is sending extra clock cycles which would throw off my Verilog counter, preventing the IOBUF from flipping at the exact moment the ADI chip responds?
Given that we are using the Zynq SPI port, but with a Verilog section that performs a transformation, do we not need a different SPI driver? (and if so, can this code be found anywhere?)
Is the adi,spi-3wire-enable option in the Device Tree sufficient to manage half-duplex mode at the software level?
Do you recommend abandoning the Verilog counter-based switching in favour of an AXI SPI IP whose tri-state (T) signal is directly controlled by the driver?