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AD9552 Recommended for New Designs
The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators...
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AD9552 on Analog.com

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AD9552: Significant Frequency Drift at Low Temperature after 1-Year Aging (Pin-Strap Mode)

		
	
				

			

									
					    cq-317
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Mar 5, 2026 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user is experiencing a critical reliability issue with the AD9552 clock multiplier in Pin-Strap mode, where the output frequency shifts higher at low temperatures after 1 year of operation. The final answer requests confirmation of procurement from an authorized distributor and asks for the A[2:0] and Y[5:0] pin states, as well as the schematic of the AD9552 and OCXO. The issue may be related to internal wear-out mechanisms or VCO characteristics shifting over time/temperature.
                        	    

                
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Category: Hardware

    		        		            		    
Product Number:  AD9552  

    		        		    		    

		    		    
		    			

			    
Dear ADI Support Team and Community,


We are encountering a critical reliability issue with the AD9552 clock multiplier in our deployed systems. We suspect a logic level interpretation error on the configuration pins due to aging and low temperature.


1. System Configuration:


    

  • Application: 6x Clock Multiplication (10 MHz input →→ 60 MHz output).
    • 

  • Input: 3.3V LVCMOS, 10 MHz from an OCXO, DC-coupled. Amplitude remains stable at low temperatures (verified by oscilloscope).
    • 

  • Configuration Mode: Pin-Strap Mode only. SPI is not connected.

      

    • Logic Levels: Pins configured for "High" are left Floating (Open). Pins configured for "Low" are pulled down to Ground.
      • 

    

    • 

  • Power Supply: Powered by an ADM7170ACPZ-3.3 LDO.
    • 

  • Loop Filter: Designed for 12nF, assembled as 10nF. (Note: Correcting this to 12nF on failed units did not resolve the issue).
    • 



2. Failure History & Statistics:


    

  • Initial Production (200 units): <5 units failed initial low-temp testing (Output >60 MHz, <65 MHz). Replacing the AD9552 fixed them.
    • 

  • Field Deployment (1 Year Later): After 1 year of continuous operation, >20% of units now fail at low temperatures (< -10°C).

      

    • Symptom: Output frequency shifts higher (>60 MHz). The drift magnitude increases as temperature drops.
      • 

    • Recovery: Frequency returns to nominal at ~0°C.
      • 

    • Chip Replacement: Swapping the AD9552 IC immediately fixes the board, functioning correctly down to -35°C.
      • 

    

    • 



3. Critical Observations & Troubleshooting:


    

  • LOCK Pin Status: We monitor the LOCK pin. During the frequency drift event at low temperature, the LOCK pin remains HIGH (indicating Locked). This suggests the PLL is locked, but potentially to an incorrect frequency due to a changed division ratio.
    • 

  • Input Signal: The OCXO output amplitude does not drop at low temperatures; drive strength is sufficient.
    • 

  • Passive Components: Replacing peripheral caps/resistors (including the loop filter) yields no improvement.
    • 

  • Power Supply: The system uses the ADM7170-3.3.
    • 



4.Our Questions:

Given that the failure appears after 1 year of aging and is triggered specifically by low temperatures in Pin-Strap mode:


    

  • Failure Mechanism: Is this indicative of a specific wear-out mechanism or internal damage within the AD9552? Could this be related to the PLL lock detector or the internal VCO characteristics shifting over time/temperature?
    • 

  • Pin-Strap Stability: Are there known issues with Pin-Strap configuration stability over long-term aging, especially compared to SPI configuration? (e.g., internal pull-up/down resistor drift affecting the decoded division ratio at low temps).
    • 

  • Recommendation: Is this considered a quality/aging issue of the silicon, or is there a marginal design condition (perhaps exacerbated by the 10nF vs 12nF loop filter initially) that accelerated this degradation?
    • 



Any insights into similar field return cases or recommended debug steps (e.g., specific registers to check if we temporarily wire up SPI) would be greatly appreciated.



			

			
									
		                             
                        

    

                                            
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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Mar 6, 2026 8:13 AM
            
            
						
			            		
    
		
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    Hi,
    

    Please confirm you procured these AD9552 devices from an Analog Devices authorized distributor. 
    

    You may enter on this website, enter AD9552 and see some lifetime data.
    

    https://www.analog.com/en/support/quality-and-reliability/reliability/wafer-fabrication-data.html 
    

    If you did procure these devices from an Analog Devices authorized distributor. then:
    

      

    1. Please tell me the A[2:0] and Y[5:0] state of frequency selection pins.
      2. 

    2.   Please send me the schematic of the AD9552 and of the OCXO
      3. 

    

    Petre
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Mar 6, 2026 10:39 PM
            
            
												
						in reply to pminc48
					
										
			            		
    
		
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    hello,
    1.Our components are procured by a top-tier SMT manufacturer in the industry, and the supplier can provide complete procurement records, ensuring the authenticity and reliability of the chip sources. Additionally, we have observed that the batch numbers of chips purchased from various legitimate channels are all 2311.
    

    

    2. A[2:0] corresponds to the 10M input, and Y[5:0] corresponds to the 60M output. The schematic diagram is shown below.
    

     
    

    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Mar 9, 2026 2:18 PM
            
            
												
						in reply to cq-317
					
										
			            		
    
		
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    Hi,
    

    I looked over the schematic and here are my notes:
    

    1) make sure the REF clock is a CMOS clock with the high level always above 1.62V. 
    

    2) The CSB pin seems to have been left floating. The data sheet states that although there is an internal pull up resistor, the pin should not be left floating. I recommend tying it up to 3.3V:
    

     
    

    When CSB is tied up, the SDIO is in high impedance, so the SDIO pin can be left floating. The SCLK has an internal pull down to ground, so it can be left floating.
    

    3) The data sheet states the capacitor on FILTER pin should be 12nF. Yet, your schematic seems to have 10nF. Please change the capacitor to 12nF
    

     
    

    4) the data sheet states to connect 0.47uF capacitors at LDO pins. Yet, you connected 1uF. Please change these capacitors to 0.47uF
    

     
    

    5) I'm not convinced the LED schematic you use is acceptable. There is no specified current that can be supported from the LOCKED pin and the eval board schematic approach makes me think the LOCKED pin cannot sustain the LED current. Please change the LOCKED schematic as in the eval board:
    

     
    

    6) Regarding the fact the OUT2 outputs have been left open: The preset settings you use enable all outputs. The eval board user guide UG-035 states to terminate all unused outputs. So my recommendation is to introduce a 100ohm resistor between OUT2 and OUT2B as this seems to be the recommended schematic
    

      
    

    7) You use an obsolete reset circuit, MAX810S. The device seems OK to me. It keeps RESET pin high as long as VCC is below 2.93V and for an additional 140ms after VCC is above 2.93V. Just make sure the VCC supply raises from around 2.93V to 3.135V (VCC min) in less than 140ms.
    

    

    You said that some boards failed during initial production. Instead of changing the AD9552 on them, make the changes I recommended above. See if the situation changes.
    

    The returned boards that failed after one year: take the AD9552 devices that failed (more of them, better it is). Contact your ADI representative. Give these and the documentation demonstrating they have been purchased through ADI authorized distributors to them and asked to be executed a failure analysis. You cannot do the same changes above on these boards because I suppose the errors above may have affected their performance.
    

    Petre
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Mar 9, 2026 8:25 PM
            
            
												
						in reply to pminc48
					
										
			            		
    
		
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    Thank you very much for your response. We acknowledge that there are numerous errors in the current schematic. Unfortunately, it is not feasible to rectify all issues via fly-wires in the current hardware version; these corrections will be implemented in subsequent revisions.
    

    

    1. Clock Signal Verification We have confirmed that the CMOS clock voltage on the REF clock pin consistently remains above 1.62V. Furthermore, the clock signal is stable and does not exhibit significant drift under low-temperature conditions.
    

    

    2. Unavailable Failed Units from Initial Production Regrettably, the circuit boards that failed immediately after initial production can no longer be located, as all components were replaced and the units have already been delivered to the customer. Initially, frequency drift at low temperatures was not a primary focus. When testers observed excessive frequency deviations in a few units, we attributed this to component quality variations and proceeded with direct replacements, which resolved the issue at the time.
    

    

    3. Failure Analysis Plan Our components were procured on our behalf by the PCB manufacturer. We will attempt to coordinate with them to retrieve the failed components and return them to your company for a comprehensive failure analysis.
    

    

    4. Temperature-Dependent Deviation Pattern For units exhibiting significant deviation at low temperatures, we have observed a clear correlation: the lower the ambient temperature, the greater the frequency deviation. Notably, all failed units observed to date show a frequency higher than expected (positive drift) under low-temperature conditions, rather than a lower frequency.
    

    

    5. Failure Observation It is worth noting that failures do not appear to occur exclusively under continuous low-temperature exposure. In a previous test batch of approximately 20 units that operated continuously indoors (at ~20°C) for over six months, one unit recently exhibited significant positive frequency drift even at room temperature. Unfortunately, this unit was also repaired by replacing the component (which restored normal operation at room temperature), and the original chip was not retained for analysis. Additionally, we recently selected another unit from this same batch (which had been operating continuously at room temperature for six months) for low-temperature testing (only one unit was tested). This unit performed normally at -25°C but exhibited positive frequency drift when tested at -35°C.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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