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AD9510 Recommended for New Designs
The AD9510 provides a multi-output clock distribution function along with an on-chip phase-locked loop (PLL) core. The design emphasizes low jitter and...
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Phase noise larger than expected based on AdiSimCLK

		
	
				

			

									
					    pkopyt
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Mar 3, 2026 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user is experiencing higher phase noise than expected when using the AD9510 evaluation board with a 25 MHz OCXO and a 100 MHz VCXO. The final answer suggests that the issue may be due to the incorrect voltage levels of the CMOS signals for the REF IN and CLK2 inputs, which exceed the absolute maximum ratings. The recommended solution is to use 50 ohm impedance and LVPECL output VCXOs, and to modify the AD9510 eval board schematic accordingly. The user should also create accurate models in ADIsimCLK for the selected components and simulate the loop filter with the provided components.
                        	    

                
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Category: Hardware

    		        		            		    
Product Number:  AD9510  

    		        		    		    

		    		    
		    			

			    
Hi Team,


I am experimenting recently with AD9510 evaluation board with a dedicated control software to upload the configuration. I am using AD9510 in a configuration where my REF is a 25 MHz signal coming from an OCXO (ECOC‑9775‑25), and my CLK2 comes from Crystek's VCXO operating at 100 MHz (CVHD-950-100). Here are the phase noise of these two parts (OCXO and VCXO, respectively):


  and  


Using the AdiSimCLK I design the loop filter for the system to get a clean 100 MHz at the output. The discrepancy between the expectations and the measurements are quite large. While the noise should go well below -150 dBc/Hz already at offsets > 10k, in my case it hovers above -150 dBc/Hz all the way up (just like this):


   


My loop filter bandwidth is ca. 1 kHz. It seems that it works, The largest differences are outside the loop bandwidth. The apparent bump @300Hz must be some artefact as measurements with a different, and typically poorer instrument (a regular spectrum analyser with phase-noise option) show a better behaviour closer to what is simulated (ca. -120 dBc/Hz @1kHz). Anyways, I hoped for a bit better numbers (closer to -160 dBc/Hz @>100k, as predicted based on VCXO behaviour far off the carrier).


My questions:


1) Are the noise floor at ca. -150 dBc/Hz something to be expected from AD9510? Could be that the increased phase noise observed in my experiments comes results from the fact that my EVAL does not have any filtering section on the DVDD/AVDD at the edge of the PCB?


2) Are there any measurements available (done with the EVAL) showing typical performance of the board (something like the phase noise curves available in catalogue notes for parts like AD9545)?


It case it matters, please find attached the session file 




    

        Fullscreen
        Test.txt
        Download
    

    
"AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00000100","04"
"07","01100000","60"
"08","01010111","57"
"09","00000000","00"
"0A","00000010","02"
"0B","00000000","00"
"0C","00000000","00"
"0D","00000000","00"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001010","0A"
"3D","00001011","0B"
"3E","00001011","0B"
"3F","00001011","0B"
"40","00000100","04"
"41","00000011","03"
"42","00000011","03"
"43","00000011","03"
"44","00010011","13"
"45","00000010","02"
"48","00000000","00"
"49","00000000","00"
"4A","00000000","00"
"4B","00000000","00"
"4C","00010001","11"
"4D","00000000","00"
"4E","00110011","33"
"4F","00000000","00"
"50","00000000","00"
"51","10000000","80"
"52","00010001","11"
"53","00000000","00"
"54","00000000","00"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00100000","20"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",25
"CLKInp1:",1200
"CLKInp2:",100
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",1





 (extension changed from .std to .txt).


Regards


Pawel

			

			
									
		                             
                        

    

                                            
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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Mar 3, 2026 3:34 PM
            
            
						
			            		
    
		
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    Hi,
    

    There are many comments here:
    

    - The ECOC‑9775‑25 output is 3.3V CMOS. The REF IN schematic of the AD9510 eval board has a balun and some load resistors. In order to function with a 3.3V CMOS, I believe that you need to take out the R48, R39 and R47. Provide the CMOS clock and put the scope probes at C41 and C42 on the side of the AD9510. I'm afraid the REFIN and REFINB voltages may go above VS+0.3V, VS=3.3V, which are the absolute max voltages and this may damage the AD9510. My recommendation is to use a regular clean signal generator that requires 50 ohm impedance on the eval board and you may use the eval board schematic as is.
    

     
    

    - The CVHD-950-100 VCXO is also a 3.3V CMOS clock. The eval board schematic is below. You have the same problems as for REFIN, but here the absolute max rating is CLK2 to CLK2B between +/-1.2V. I'm pretty sure modifying the schematic and then using a 3.3V CMOS will not work. You need to find a VCXO that can meet the conditions from the data sheet
    

     
    

     
    

    - I believe the schematic of the U8 VCXO on the eval board was designed for a VCXO Epson Toyo TCO-2112 VCXO, 245.76MHz, LVPECL outputs. So my recommendation is to find a 100MHz VCXO that has LVPECL outputs as well 
    

    - I am therefore not sure the phase noise plot of the AD9510 output has any meaning.
    

    - About the ADIsimCLK simulation: 
    

      

    • once you settle on the REFIN and on the CLK2 VCXO, you need to create models for these in the ADIsimCLK. Use the help of the tool to guide you through the process. 
      • 

    • then you can do the simulation. I would use the components that are in the loop filter schematic for U8 to see how the simulation works. Then you can play with other parameters
      • 

    •  
      • 

    

    Petre
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Mar 4, 2026 8:45 AM
            
            
												
						in reply to pminc48
					
										
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi Petre,
    

    Many thanks for the reply.
    

    I have just checked the REF IN on the side of the IC. What I got there is the internal DC biasing voltages that agree with the specs (i.e. ca. 1.5V). The AC signal there is around 100 mVp-p, which looks good compared to the specs. Certainly, I do not exceed the 2Vp-p listed in the specs as maximum values allowed.
    

    As for the CLK2 input, we have connected the CVHD-950-100 VCXO by placing it as U8 (the footprints match). Here are the details:
    

     
    

    So in our case the VCXO outputs a single-ended signal that is routed over CLK2_1 nets. It then goes to the T3 balun and is differentially routed to the IC, like this:
    

     
    

    Like I say, the DC voltage measured with an oscilloscope on the C48/C47 (on the chip's side), as well as on the C41/C42 show AC voltage levels of ca. 100's mV. Also by keeping the differential signal patch on the input we hoped for reduced common mode noise that would degrade the phase-noise performance.
    

    As for the AdiSimCLK simulations, I do not expect that there is anything wrong there. Analysing the bahaviour of the chip (simulated) within the loop bandwidth it looks OK, and moreover it agrees reasonably well with measurements. What worries me is the noise level outside of the bandwidth. Are there any exemplary phase-noise curves for an output signal close to 100 MHz to make some comparisons?
    

    Regards
    

    Pawel
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Mar 5, 2026 9:41 AM
            
            
												
						in reply to pkopyt
					
										
			            		
    
		
										+1
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi,
    

    it's not clear to me why when the 3.3V CMOS clock is applied AC coupled to the CLK2 balun creates a voltage of 100mV peak(?). I would expect a bigger value. There is a resistor drawn in green without any value in you schematic that may be a 50ohm one and that may reduce the voltage to acceptable levels. The CMOS drivers are not designed to drive 50ohm loads. Using them as such may affect negatively the phase noise. 
    

    " Are there any exemplary phase-noise curves for an output signal close to 100 MHz to make some comparisons?"
    

    The AD9510 data sheet presents only additive phase noise plots. From the stp file you sent, it seems you enabled OUT4=100MHz LVDS, so you may have measured the phase noise at an LVDS output. The figure 28 represents the case of the 122.88MHz LVDS additive phase noise.
    

    I took an AD9510 eval board equipped with that Toyo VCXO of 245.76MHz and I configured it to output 245.76MHz clock while receiving a 245.76MHz, 3dBm clock from a Rohde & Schwartz SMA 100A generator.
    

    I configured it as in the attached (take out the txt extension if you want to load it into the eval software). I got the lock indicator to indicate lock.
    

    



    
    
    
        Fullscreen
        AD9510_245p76M_VCXO_setup.stp.txt
        Download
    
    
    
    "AD9510 Setup File"
"Rev","1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"00","00010000","10"
"02","00100000","20"
"04","00000000","00"
"05","00000000","00"
"06","00000100","04"
"07","00000000","00"
"08","01000111","47"
"09","01110000","70"
"0A","00011010","1A"
"0B","00000000","00"
"0C","10000000","80"
"0D","00000000","00"
"34","00000001","01"
"35","00000000","00"
"36","00000000","00"
"37","00000100","04"
"38","00000001","01"
"39","00000000","00"
"3A","00000000","00"
"3B","00000100","04"
"3C","00001010","0A"
"3D","00001000","08"
"3E","00001000","08"
"3F","00001000","08"
"40","00000010","02"
"41","00000010","02"
"42","00000011","03"
"43","00000011","03"
"44","00010011","13"
"45","00000000","00"
"48","00000000","00"
"49","00000000","00"
"4A","00000000","00"
"4B","00000000","00"
"4C","00000000","00"
"4D","00000000","00"
"4E","00110011","33"
"4F","00000000","00"
"50","00000000","00"
"51","00000000","00"
"52","00010001","11"
"53","00000000","00"
"54","00000000","00"
"55","00000000","00"
"56","00000000","00"
"57","00000000","00"
"58","00000000","00"
"59","00000000","00"
"5A","00000000","00"
""
"Other Settings..."
"RefIn:",245.76
"CLKInp1:",1200
"CLKInp2:",245.76
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",1

    

    


    

    Comparing the configuration with yours: I used a much higher feedback divider than you because I wanted to use the prescaler at 32/33. If you got the PLL to indicate lock with a feedback divider set to 4, it is fine.
    

    I got this phase noise plot for the 245.76MHz LVPECL output. I had to use the LVPECL output and not the LVDS because on my board, the LVDS outputs were all DC coupled. Only OUT2=245.76MHz was LVPECL AC coupled.
    

     
    

    You can infer the 100MHz phase noise by adjusting all measurements by 20*log10(100MHz/245.76MHz). You cannot adjust the noise floor, so I believe you need to consider the noise floor as being around -152 dBc/Hz.
    

    Petre
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Mar 10, 2026 6:04 AM
            
            
												
						in reply to pminc48
					
										
			            		
    
		
										+1
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    Hi,
    

    Many thanks for the detailed answet and the experiment you did. The resistor in my schamatics (the one marked in green) is 100 Ohm and you are right that it reduces the volatage at the AD9510 input to acceptable levels. 
    

    Based on the phase-noise curve you measured it seems that the phase-noise floor (at large offsets) could be ca. -150 dBc/Hz, close to what I got with me tinkered evaluation board. Thanks a lot -- this confirms that there is not much point in trying to go lower with noise, with a small exception of improvements with regards to the OCXO output circuit and routing of the signal the CLK2 input.
    

    Best Regards
    

    Pawel
    

    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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