In AD9528, according to the Detailed block diagram, the SYSREF_IN signal can be retimed by PLL1 or PLL2 output, or not retimed at all. This is coherent with Evaluation Software, and
- register 0x402, bit 3 "Resample clock source for external SYSREF",
- register 0x403, SYSREF source.
But, how is it possible that registers 0x300, 0x303, ... allow for each output independently to choose between
- SYSREF (retimed by PLL2 output)
- SYSREF (retimed by PLL1 output).
- SYSREF (retimed by inverted PLL1 output).
?



