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Sysref retimed in AD9528: how many options?

Thread Summary

The user inquires about the retiming of the SYSREF_IN signal by PLL1 or PLL2 outputs, as controlled by registers 0x300, 0x303, etc. The final answer confirms that retiming at the SYSREF_IN input ensures synchronization with VCO_IN or the PLL feedback clock, while the output retiming options allow for generating DEVCLK and SYSREF synchronously. The registers 0x402 and 0x403 are also mentioned for configuring the resample clock source and SYSREF source.
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Category: Datasheet/Specs
Product Number: AD9528

In AD9528, according to the Detailed block diagram, the SYSREF_IN signal can be retimed by PLL1 or PLL2 output, or not retimed at all. This is coherent with Evaluation Software, and

  • register 0x402, bit 3 "Resample clock source for external SYSREF",
  • register 0x403, SYSREF source.

But, how is it possible that registers 0x300, 0x303, ... allow for each output independently to choose between

  • SYSREF (retimed by PLL2 output)
  • SYSREF (retimed by PLL1 output).
  • SYSREF (retimed by inverted PLL1 output).

?

  • Hi,

    I'm not sure I understand very well the issue you are emphasizing, but I'll try to give you some comments:

    There is retiming at the SYSREF_IN input (page 34 in rev G data sheet)

    This retiming solves the problem of the SYSREF_IN coming into the device in a non synchronous manner relative to the VCO_IN clock or the PLL feedback clock after the N divider. 

    Then there is retiming at the outputs, with selections from the registers 0x300, etc as you point out. These choices help to generate DEVCLK and SYSREF synchronously

    Petre

  • Thank you for your answer.

    You mean there is an optional retiming at the input, and then a mandatory retiming at the output? Sorry, I did not look carefully at the Detailed bloc diagram. I can see it now, but only partially:

    • The option "retimed by inverted PLL1 output" is not visible on the Detailed bloc diagram. Ok, I understand.
    • According to the Detailed bloc diagram the SYSREF signal could be not retimed at all, but this option is not present in the description of register 0x300, 0x303, ...
    • In the Evaluation software the different retiming options at the output can not be chosen.
  • Hi,

    these retimings are not mandatory. You do what is necessary for your application.

    The detailed block diagram cannot show every single functionality detail. This is why the data sheet contains other figures.

    "In the Evaluation software the different retiming options at the output can not be chosen. "

    In the eval software, select the group of outputs first from the  Distribution Bank Selector and then click DIST REGISTERS button. Then the Buffer Source drop down menu shows the retiming options:

    Then click Load.

    Petre

  • Ok. But in the "Distribution Bank" the option "Sysref" (not retimed) corresponds to which value of register 0x300? When I select it and save the Setup File, there is no change in the file.

  • Hi,

    I went into the eval software and I changed OUT0 Buffer Source going down the menu. I also opened the Register Map Window and I followed the settings of register 0x300. I found that:

    Buffer Source Menu Register 0x300 Bits 7:5 of register 0x300 Register 0x32D Bits 7:1 meaning of register 0x32D
    Divider Output 0x00 000, PLL2 Divider Output 0x00
    PLL1 Output 0x20 001, PLL1/VCXO Output 0x00
    Inverted PLL1 Output 0xA0 101, Inverted PLL1/VCXO Output 0x00
    SYSREF 0x40 010, SYSREF (retimed by PLL2 output) 0x02 Channel 0 bypass SYSREF resample
    SYSREF (retimed by PLL1 Output) 0x60 100, PLL2/divider output 0x00
    SYSREF(retimed by inverted PLL1 output) 0xE0 111, SYSREF(retimed by inverted PLL1 output) 0x00
    SYSREF (retimed by divider output) 0x40 010, SYSREF (retimed by PLL2 output) 0x00

    So you can see that to get not retimed SYSREF, you have to set bits 7:5 in 0x300 as 010 and then set bit 1 in register 0x32D .

    This is why we recommend to use the eval software to configure the AD9528 in order to get the register map.

    After I set the register 0x300 to 0x40, I saved the configuration. I then compared the stp file against the initial one I had loaded and I found the register 0x300 has this new value. So I was not able to confirm your statement that changing the options in the Buffer Source Menu does not change the stp file.

    Petre

  • It is clear now. Thank you very much @. Sorry for my misunderstanding. Indeed almost impossible to infer without eval software.