Category: Hardware
Product Number: AD9914
Hello,
I am using an AD9914 DDS with a 3 GHz external reference clock applied directly to the REFCLK input. The internal PLL is disabled and all PLL-related pins are left unused.
I am observing an intermittent issue with the output signal:
The desired output is a stepped amplitude profile (looks correct when working properly).
However, sometimes the output appears distorted.
The distortion manifests as ripple and unstable amplitude levels within each step.
The frequency is correct, but the amplitude is not stable.
The noise floor looks normal.
The step shape is correct, but the flat tops are not clean.
Important observation:
If I disable and re-enable the 3 GHz reference clock, the output immediately becomes correct and stable again.
This strongly suggests that the issue is related to the REFCLK domain rather than the DAC output stage or reconstruction filter.
System details:
REFCLK frequency: 3 GHz
Internal PLL: Disabled
REFCLK applied directly to the device
Differential clock input
Proper termination implemented (100 Ω differential)
Power supplies appear stable (no obvious large ripple observed)
Questions:
Has anyone experienced unstable behavior when driving AD9914 directly with a 3 GHz reference clock (PLL disabled)?
Are there known sensitivity issues at the upper REFCLK frequency limit?
Could this be related to input amplitude window or common-mode biasing?
Is there a recommended reset or initialization sequence when operating at 3 GHz REFCLK?
Any insights or similar experiences would be greatly appreciated.
Thank you.
