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AD9213-DUAL-EBZ: LTC6946 settings

		
	
				

			

									
					    roddyvann
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Feb 5, 2026 
				
			
			
		

		
		                     
				
        		

		    
		    		    

		      		            		        
Category: Hardware

    		        		            		    
Product Number:  AD9213S  

    		        		    		    

		    		    
		    			

			    
Hi folks


I have purchased a AD9213-DUAL-EBZ and I'm pairing it with a Xilinx VMK180. I am struggling a bit with the LTC6946/LTC6952 pairing - I can't get the LTC6952 to lock its PLL. Please might you supply the register settings for the 6946 that you use in the design with the Stratix board? I have the 6952 settings from that design's DTS but can't find any scripts or lists of settings for the 6946. Please might you help me?


Thank you!


Roddy

			

			
									
		                                 
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                 Clock Generation Devices
                
                                                    
                 Phase-Locked Loop (PLL) Synthesizers
                
                                                    
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    •  Analog Employees  
    •  Super User  
    
            
						
                            
            
            				
            
                on Feb 5, 2026 10:21 PM
            
            
						
			            		
    
		
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    Moving this question to the Clocks & Timers forum. Someone here should be able to assist you.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Feb 6, 2026 5:19 PM
            
            
						
			            		
    
		
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    Just in case it's helpful, I have attached the contents of the LTC6946 registers and the LTC6952 DTS section. The LTC6952 driver shows in dmesg:
    ltc6952 spi3.1: CLKIN: 3750.000000 MHz REFIN: 500.000000 MHz REF: Valid VCO: Valid PLL: Unlocked



    
    
    
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        ltc6952_DTS_snippet.txt
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    	ltc6952: ltc6952@1 {
		compatible = "adi,ltc6952";
		reg = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		spi-max-frequency = <1000000>;
		jesd204-device;
		#jesd204-cells = <0x02>;
		jesd204-sysref-provider;
		clock-output-names = "ltc6952_out0", "ltc6952_out1",
				"ltc6952_out2", "ltc6952_out3", "ltc6952_out4",
				"ltc6952_out5", "ltc6952_out6", "ltc6952_out7",
				"ltc6952_out8", "ltc6952_out9", "ltc6952_out10";
		#clock-cells = <1>;
		adi,vco-frequency-hz = <3750000000>; /* = 3.75 GHz = <0xdf847580>; */
		/* adi,ref-frequency-hz = <250000000>; */ /* = 250 MHz */
		adi,ref-frequency-hz = <500000000>; /* = 500 MHz */
		adi,charge-pump-microamp = <1000>; /* another file has <3370> for for vco=1.25GHz & vref = 1000MHz */

		channel@0 {
			reg = <0x00>;
			adi,extended-name = "SYSREF_0";
			adi,divider = <0x300>; /* => sysref = 4.8828125 MHz = (device clock) / JESD_N / JESD_K */
			adi,digital-delay = <0x00>;
			adi,analog-delay = <0x00>;
			adi,sysref;
		};

		channel@1 {
			reg = <0x01>;
			adi,extended-name = "SYSREF_1";
			adi,divider = <0x300>;
			adi,digital-delay = <0x00>;
			adi,analog-delay = <0x00>;
			adi,sysref;
		};

		channel@4 {
			reg = <0x04>;
			adi,extended-name = "CLK_COPY"; /* CLK_COPY or GLBLCLK or LA00_CC*/
			adi,divider = <0x0c>; /* => 312.5 MHz */
			adi,digital-delay = <0x00>;
			adi,analog-delay = <0x00>;
		};

		channel@5 {
			reg = <0x05>;
			adi,extended-name = "SYSREF_COPY"; /* SYSREF_COPY or LA02 */
			adi,divider = <0x300>;
			adi,digital-delay = <0x00>;
			adi,analog-delay = <0x00>;
		};

		channel@6 {
			reg = <0x06>;
			adi,extended-name = "FMC_P1_GBTCLK1M2C";
			adi,divider = <0x0c>;
			adi,digital-delay = <0x00>;
			adi,analog-delay = <0x00>;
		};

		channel@7 {
			reg = <0x07>;
			adi,extended-name = "FMC_P1_GBTCLK3M2C";
			adi,divider = <0x0c>;
			adi,digital-delay = <0x00>;
			adi,analog-delay = <0x00>;
		};

		channel@8 {
			reg = <0x08>;
			adi,extended-name = "FMC_P2_GBTCLK1M2C";
			adi,divider = <0x0c>;
			adi,digital-delay = <0x00>;
			adi,analog-delay = <0x00>;
		};
		
		channel@9 {
			reg = <0x09>;
			adi,extended-name = "FMC_P2_GBTCLK3M2C";
			adi,divider = <0x0c>;
			adi,digital-delay = <0x00>;
			adi,analog-delay = <0x00>;
		};
	};

    

    





    
    
    
        Fullscreen
        ltc6946_status.txt
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    LTC6946-2 status: LOCK=1, UNLOCK=0, ALC[HI/LO]=0/1, TUNE[HI/LO]=0/0
Dividers: O=1, R=3, N=45 | fPFD=83.333333 MHz, fVCO=3750.000000 MHz, fOUT=3750.000000 MHz
0x00 0x33
0x01 0x04
0x02 0x00
0x03 0xf0
0x04 0x01
0x05 0x2d
0x06 0xfa
0x07 0x61
0x08 0x39
0x09 0x9b
0x0a 0xe4
0x0b 0x62

    

    


    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Feb 6, 2026 6:00 PM
            
            
						
			            		
    
		
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    It hasn't fixed the problem, but I had a bug in my LTC6946 script, which I have now fixed, so my LTC6946 registers (which still don't work) are:
    LTC6946-2 status: LOCK=1, UNLOCK=0, ALC[HI/LO]=0/0, TUNE[HI/LO]=0/0
    Dividers: O=1, R=3, N=45 | fPFD=83.333333 MHz, fVCO=3750.000000 MHz, fOUT=3750.000000 MHz
    0x00 0x22
    0x01 0x04
    0x02 0x00
    0x03 0xf0
    0x04 0x03
    0x05 0x00
    0x06 0x2d
    0x07 0x61
    0x08 0x39
    0x09 0x9b
    0x0a 0xe4
    0x0b 0x62

    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Feb 7, 2026 12:36 PM
            
            
						
			            		
    
		
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    I've now found the LTC6946 settings for this project: they are in the altera_adxcvr_master branch of the Analog Devices kernel source, file ltc6946.c
    (Sorry for wasting anyone's time with this.)
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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