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HMC7043 Not Recommended for New Designs
The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution...
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HMC7043 on Analog.com

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Regarding Unwanted Short Pulse Waveforms Occurring in the Output Waveform of the HMC7043

		
	
				

			

									
					    baggio
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Feb 4, 2026 
				
			
			
		

		
		                     
				
        		

		    
		    		    

		      		            		        
Category: Hardware

    		        		            		    
Product Number:  HMC7043  

    		        		    		    

		    		    
		    			

			    
The EVAL-HMC7043 is operating with the following settings.


　・CLK IN = 200MHz


　・Divider = 50


   ・SCLKOUT1 = 4MHz


　・OUTPUT = CML


I'm attaching the configuration file.


If Digital Delay is 0 at this time, the output of SCLKout1 will be fine.


Next, when the Digital Delay setting was set to 17, a short pulse-like waveform was observed.


 


Is there a way to avoid this symptom?


Best Regards.




test1.zip

			

			
									
		                             
                        

    

                                            
                 Clock Generation and Distribution
                
                                                    
                 hardware
                
                                                    
                 Clock Distribution Devices
                
                                                    
                 hmc7043
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

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                on Feb 16, 2026 10:21 PM
            
            
						
			            		
    
		
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    Hello. I also tried an additionaly RFsync test.
    

    However, this issue alos occurred in RFsync test.
    

    This is the waveform from that time.It occurs when digital delay is increased. I attaching the configulation file.
    

     Looking at this waveform, it appears that the previous SCLK1 signal waveform is being output as SCLK1.
    

    Could you explain why it behaves this way?
    

     
    

    

    Best Regards.
    

    test2_RFsync.zip
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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