I have experience in FPGA but new to SDR and apologize if making dumb questions.
I am defining parts for an 8-channel MIMO prototype device and planning to use two AD-FMCOMMS8-EBZ boards and an AMD Kria K26 on a custom carrier. The total bit rate from each ADRV9009 is expected to be 2.4576 Gb/s.
The K26 has only 4 high-speed SERDES lanes available (GTH), so my question is:
Can I leverage JESD lane sharing and connect just one JESD lane from each ADRV9009? In other words, can I connect only JESD_SERDOUT0_C and JESD_SERDOUT0_D lanes from each AD-FMCOMMS8-EBZ board?
Besides, each AD-FMCOMMS8-EBZ board has an HMC7044 clocking device. Is it possible to leverage one or both to synchronize the 8 channels without adding a third clocking device on the carrier?
I am not asking you to give details on how to do these jobs, please just confirm whether they are doable or not.
Thank you in advance and find regards.
