Cannot achieve SPI readback

Trying to configure the HMC7044, I realized it only sometimes reads back from registers correctly. I was using 4-wire SPI mode by configuring GPIO2 as SDATA out, using a 500kHz clock. I verified that I had control of some aspects of the part by configuring it to generate the clock output that I wanted, changing the frequency of the clock output, and configuring GPIO1 to output a logic 1, then to 0, then back upon request. I then reduced my debug scope to only validating SPI commnication.

The steps of this first test were as follows:

1. Issue hardware reset
2. Write 0x7 to register 0x51
3. Write 0x0 to register 0x54
4. Write 0xB4 to register 0x8
5. Read register 0x8

I do not have screenshots from the oscilloscope of this test.

Next, I tried updating the reserved register configuration:

1. Issue a hardware reset
2. Write 0x4D to register 0x9F
3. Write 0xDF to register 0xA0
4. Write 0x6 to register 0xA5
5. Write 0x4 to register 0xB0
6. Write 0x7 to register 0x51
7. Write write 0x0 to register 0x54
8. Write 0xB4 to register 0x8
9. Read register 0x8

I then rebuilt the FPGA to control SLEN, in case the large delay between SLEN assertion in software and rising edge on SCLK was a problem. With this configuration, I tried the same test again, but got the same intermittent (mostly failing) results.

Finally, I rebuilt the FPGA again to use 3-wire SPI mode, and tried the most simple communication I could think of, using the default configuration:

1. Issue a hardware reset
2. Write 0xB4 to register 0x8
3. Read register 0x8

The results follow:

Zoomed out so that you can see SLEN (Non-deterministic time between assertion, since it is once again controlled via software).

The same thing again, but zoomed in so you can see the quality of the transaction:

Is there more to configuring the SPI communication that I'm not seeing?