Hello,
We are using two HMC7044 clock chips to provide clock inputs to eight ADC chips. Each HMC7044 distributes a 122.88 MHz clock to four ADCs, and all ADCs receive this reference clock from the same source.
The HMC7044 initialization code we are using was taken from the Analog Devices official GitHub repository.
Our goal is to ensure that the ADC output data maintains a consistent phase relationship across all devices, even across power cycles. However, we have observed that ADC phases vary from power-on to power-on, which is a critical issue for our application.
Requirements:
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Clock outputs within each HMC7044 must be phase-aligned and maintain a constant phase relationship across power cycles.
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Both HMC7044 chips must be synchronized so that their outputs are also phase-aligned.
Issue with Requirement 1 – Internal Clock Alignment
We probed the clock outputs of individual HMC7044 devices and observed that the outputs are not phase-aligned after each power-on. The phase relationship between outputs also varies from reset to reset.
To address this, after completing the HMC7044 initialization using the ADI GitHub code, we issued a reset (resync) pulse by setting bit 1 of register 0x005B to logic 1, then clearing it to 0 after a short duration. We then read back register 0x007D, and observed the value 0x13, which indicates that PLL2 is not synchronized and the phase output is unstable.
We need help understanding:
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Why PLL2 is not synchronizing,
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And how to ensure that all output dividers within each HMC7044 are phase-aligned.
Issue with Requirement 2 – Multi-Chip Synchronization
We understand that multi-chip synchronization can only succeed if the individual HMC7044 devices are internally aligned first.
Assuming we resolve the internal alignment issue, we would like to confirm:
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Is applying a simultaneous one-shot SYNC pulse to both HMC7044 chips (after initialization) sufficient for multi-chip synchronization?
Request
We are currently blocked due to these phase alignment issues, which are critical to our system performance. Despite referring to documentation and community forums, we have not yet found a working solution.
Could you please provide:
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A clear, step-by-step sequence to achieve both internal phase alignment within each HMC7044 and cross-chip synchronization?
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Any register configurations or timing considerations we may have missed?
We appreciate your support in resolving this issue.
Best regards
