System Clock reference oscillator choice

Hi,

this is what we recommend as of today:

- use a 52 MHz crystal resonator to create the AD9545 system clock. The maintaining amplifier that uses the resonator at its inputs ensures an output clock has a perfect 50% duty cycle. This clock is then applied to a doubler, which basically requires a 50% duty cycle clock to function perfectly. Then the system clock PLL likes a 50% duty cycle clock to create a lowest phase noise possible system clock. This is then reflected on the phase noise of the AD9545 outputs as this approach makes the phase noise to be at the lowest possible level.

- we also played with even higher frequency crystals, but the improvements relative to 52MHz case were not significant, so we settled on recommending the 52MHz crystal for bet AD9545 phase noise performance. 

- The OCXOs or TCXOs have a duty cycle specification between 45% and 55%. The doubler then cannot be used and the phase noise performance of the system clock PLL and consequently of the AD9545 outputs worsens. This is why we introduced this comment in the specifications table:

Bottom line: we recommend using the 52MHz crystal resonator to create the system clock. Use the OCXO or TCXO to stabilize the effects of the resonator wonder at TDCs, DPLLs and AuxNCOs using the system clock compensation scheme #3 (with AuxDPLL). Just apply it at one of the REFA, REFAA, REB or REFBB inputs, or if the clock is VDDIOx CMOS, apply it at one of Mx pins.

Petre

Hi Petre,

thank you very much for the quick response but I would like to ask one more question: when using crystal resonator for the system clock is there any risk of spurs very close to the carrier frequency of this system clock to appear due to rather poor short-term stability caused by the crystal resonator? When we used recently similar IC but from different vendor we observed that when crystal oscillator instead of e.g. OCXO was used then spurs in the very narrow span and RBW using SA (ca. 50 - 200 Hz)  could be observed around carrier frequency but when crystal was replaced with stable OCXO they disappeared.

Best regards.

Hi,

If you look at the typical performance phase noise plots in the data sheet, I do not see spurs. Of course, the instrument may have been set to not show them. I do not know.

I set the AD9545 to generate in freerun 245.76MHz, HCSL, 7.5mA ( close frequency to the 5th harmonic of 52MHz) and I obtained this:

There are two very small spurs, at 1.36MHz and 4.17MHz, but I am not convinced they are a problem.

If you apply the system clock compensation scheme with the AuxDPLL, no spurs will be created based on the OCXO.

Petre

Hi Petre,

thank you so much for you support and help.

Best regards.