Configuring Individual Channels for CLK/SYSREF Modes on HMC7043 Evaluation Board

Hi, 

On the HMC7043, all channels are identical. There is no difference between CLKOUT vs sCLKOUT channels.

They can be configured either  as CLK channels/Continuous (Asynchronous mode) or as N-Pulse SYSREF/Pulse Generation (Dynamic mode).

Please note that Evaluation board is configured to have LVPECL termination on the even numbered clock outputs. 

Here is the setting location in GUI: 

After that, you need to set the MUTE SEL bit. This bit should be set to Logic 0 at idle when channel is configured in dynamic mode. 

You need to the set the Sysref Timer Enable and Sysref Timer divider value. Under Pulse control, you can set the number of pulses to generate. IT can be level sensitive, which means dynamic channels are active as long as SYNC input is 1 or pulsor bit is 1. 

It can have certain number of pulses. Number of pulses that a channel can generates depends on sysref timer value and channel divider value.
Here is the calculation: 

The number of pulses generated depends on the channel divider and SYSREF timer value.

Pulse count can be calculated as follows:

If MultiSlip Bit is enabled:  Pulse # = ((m+1)*n)

If Multislip Bit is disabled:  Pulse # = ((m+1)*n)-1

where m: number of pulses set by register 0x005A
and n: <SysRef Divider> / <Channel Divider> (should be an integer)

Continuous mode on the pulsor control glitches the Synchronization FSM. Pulse generator timeout never
ends. We recommend using asynchronous mode if continuous SYSREF is needed.

Thanks,

Emrecan